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2010 – 2019
- 2018
[c106]Bastien Deveautour, Arnaud Virazel
, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman:
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS 2018: 1-6- 2016
- [j29]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - 2015
- [c105]Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - 2014
- [j28]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j27]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [c104]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c103]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - 2013
- [c102]Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c101]Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c100]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné:
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c99]Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS 2013: 1-4 - 2012
- [j26]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. J. Electron. Test. 28(2): 215-228 (2012) - [j25]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28(3): 317-329 (2012) - [c98]Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Advanced test methods for SRAMs. VTS 2012: 300-301 - 2011
- [c97]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c96]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 - [c95]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 - [c94]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 - [c93]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 - [c92]Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch:
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232 - [c91]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 - [c90]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda:
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158 - [c89]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 - 2010
- [j24]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [j23]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) - [c88]Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo:
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 - [c87]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 - [c86]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 - [c85]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c84]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169 - [c83]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 - [c82]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. ETS 2010: 81-86 - [c81]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS 2010: 132-137 - [c80]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Setting test conditions for improving SRAM reliability. ETS 2010: 257 - [c79]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805 - [c78]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c77]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80
2000 – 2009
- 2009
- [j22]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. 25(2-3): 127-144 (2009) - [j21]Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3(6): 581-592 (2009) - [j20]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1556-1559 (2009) - [c76]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 - [c75]Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348 - [c74]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55 - [c73]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 - [c72]Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 - [c71]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard:
NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 - 2008
- [j19]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24(4): 353-364 (2008) - [c70]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485 - [c69]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325 - [c68]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 - [c67]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 - [c66]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 - [c65]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 - [c64]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 - [c63]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94 - 2007
- [j18]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. 23(5): 435-444 (2007) - [c62]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Fast Bridging Fault Diagnosis using Logic Information. ATS 2007: 33-38 - [c61]Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel:
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS 2007: 507-510 - [c60]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533 - [c59]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 - [c58]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis. ETS 2007: 13-20 - [c57]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS 2007: 77-84 - [c56]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS 2007: 97-104 - [c55]Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga:
A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10 - [c54]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52 - [c53]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368 - 2006
- [j17]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22(1): 89-99 (2006) - [j16]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. 22(2): 161-172 (2006) - [j15]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. 22(3): 287-296 (2006) - [c52]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault:
Power-Aware Test Data Compression for Embedded IP Cores. ATS 2006: 5-10 - [c51]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 - [c50]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 - [c49]Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113 - 2005
- [j14]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. 21(1): 43-55 (2005) - [j13]Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. 21(2): 169-179 (2005) - [j12]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. 21(5): 551-561 (2005) - [c48]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862 - [c47]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS 2005: 116-121 - [c46]Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549 - [c45]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281 - [c44]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188 - 2004
- [j11]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20(6): 647-660 (2004) - [c43]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271 - [c42]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 - [c41]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88 - [c40]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 - [c39]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS 2004: 52-57 - [c38]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS 2004: 140-145 - [c37]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192 - [c36]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138 - 2003
- [c35]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255 - [c34]Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Defect-oriented dynamic fault models for embedded-SRAMs. ETW 2003: 23-28 - [c33]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW 2003: 147-152 - [c32]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128 - [c31]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 - 2002
- [j10]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19(5): 44-52 (2002) - [j9]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18(2): 145-157 (2002) - [c30]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449 - [c29]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803 - [c28]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On Using Efficient Test Sequences for BIST. VTS 2002: 145-152 - 2001
- [j8]Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. 17(3-4): 233-241 (2001) - [c27]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 - [c26]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On hardware generation of random single input change test sequences. ETW 2001: 117-123 - [c25]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 - [c24]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89 - [c23]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 - 2000
- [j7]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16(3): 193-202 (2000) - [c22]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464 - [c21]Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay fault testing: choosing between random SIC and random MIC test sequences. ETW 2000: 9-14 - [c20]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126 - [c19]Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661
1990 – 1999
- 1999
- [j6]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. 14(1-2): 95-102 (1999) - [c18]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 - [c17]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. ETW 1999: 165-170 - [c16]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24- - [c15]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 - [c14]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412 - 1998
- [c13]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439 - 1997
- [j5]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac:
A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. 24(1): 37-52 (1997) - [c12]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac:
A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286 - [c11]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch:
An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100 - 1996
- [c10]P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC 1996: 79-87 - [c9]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293 - [c8]S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A new test pattern generation method for delay fault testing. VTS 1996: 296-301 - 1995
- [j4]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. 6(3): 277-294 (1995) - [j3]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
Delay fault diagnosis in sequential circuits based on path tracing. Integr. 19(3): 199-218 (1995) - [c7]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC 1995: 526-533 - [c6]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386 - 1994
- [c5]D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523 - 1993
- [c4]D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713 - 1992
- [j2]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. 9(4): 27-32 (1992) - [c3]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360 - [c2]Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A New Reliable Method for Delay-Fault Diagnosis. VLSI Design 1992: 12-16 - 1991
- [j1]Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. 2(3): 229-241 (1991) - 1990
- [c1]Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
Fault modelling and fault equivalence in CMOS technology. EURO-DAC 1990: 407-412
Coauthor Index
[j29] [c105] [j28] [j27] [c104] [c103] [c102] [c101] [c100] [c99] [j26] [j25] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [j24] [j23] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j21] [c76] [c74] [c73] [c72] [c71] [c69] [c68] [c67] [c66] [c65] [c64] [c62] [c59] [c58]
[c106] [j29] [c105] [j28] [j27] [c104] [c103] [c102] [c101] [c100] [c99] [j26] [j25] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [j24] [j23] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j22] [j21] [j20] [c76] [c75] [c74] [c73] [c72] [c71] [j19] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [j18] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j17] [j16] [j15] [c52] [c51] [c50] [c49] [j14] [j13] [j12] [c48] [c47] [c46] [c45] [c44] [j11] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j10] [j9] [c30] [c29] [c28] [j8] [c27] [c26] [c25] [c24] [c23] [j7] [c22] [c21] [c20] [c19] [j6] [c18] [c17] [c16] [c15] [c14] [c13] [j5] [c12] [c11] [c10] [c9] [c8] [j4] [j3] [c7] [c6] [c5] [c4] [j2] [c3] [c2]
[j22] [j21] [j19] [c68] [c67] [c66] [c64] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j17] [c52] [c50] [c49] [c46] [c45] [j11] [c42] [c40] [c31] [j10] [j9] [c30] [c29] [c28] [j8] [c27] [c26] [c25] [c24] [c23] [j7] [c22] [c21] [c20] [c19] [j6] [c18] [c17] [c16] [c15] [c14] [c13] [j5] [c12] [c11] [c10] [c9] [c8] [j4] [j3] [c7] [c6] [c5] [c4] [j2] [c3] [c2] [j1] [c1]
[c106] [j29] [c105] [j28] [j27] [c104] [c103] [c102] [c101] [c100] [c99] [j26] [j25] [c98] [c97] [c96] [c95] [c94] [c93] [c91] [c90] [c89] [j24] [j23] [c88] [c87] [c86] [c85] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j22] [j21] [j20] [c76] [c75] [c73] [c72] [c71] [j19] [c70] [c68] [c67] [c66] [c65] [c64] [c63] [j18] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j17] [j15] [c51] [c50] [c49] [j13] [j12] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c40] [c38] [c36] [c35] [c34] [j10] [j9] [c28] [j8] [c26] [c25] [c21] [c20] [j6] [c13]
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