11th DDECS 2008: Bratislava, Slovakia

Invited Presentations

Poster Session I

Process Variations Aware Design

Physical Design

ATPG and Fault Tolerance

SoC and NoC Design

Digital Design Methods

Poster Session II

ASIC and FPGA Design

Student Papers

Design Verifications

Industrial Papers I

Industrial Papers II

Poster Session III

Analog Test

BIST and Mems Test

SoC and Memory Test

maintained by Schloss Dagstuhl LZI at University of Trier