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ORCIDReza Hashemian
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2020 – today
- 2024
[j16]Reza Hashemian
:
Extended "A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits". IEEE Trans. Circuits Syst. II Express Briefs 71(2): 503-507 (2024)- 2022
- [j15]Reza Hashemian:
A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2819-2831 (2022) - [j14]Reza Hashemian:
Quick Access to Circuit Transfer Functions via NAM Determinant/Cofactors Using UaL Technique. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 689-693 (2022) - 2021
- [c20]Reza Hashemian:
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method. ISCAS 2021: 1-5 - 2020
- [j13]Reza Hashemian:
UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 630-634 (2020) - [c19]Reza Hashemian:
Constructing Circuit Transfer Functions directly from the State Equations, Using Convolutions. EIT 2020: 265-270 - [c18]Reza Hashemian:
s-Expanded Transfer Function using UaL Decomposition with Convolution & Deconvolution. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c17]Reza Hashemian:
Design of Analog Circuits for Continuously Changing Constraints Using Fixator Norator Pairs. MWSCAS 2019: 658-661 - 2018
- [j12]Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian:
Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits. J. Circuits Syst. Comput. 27(3): 1850050:1-1850050:11 (2018) - [j11]Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian:
A nullor approach to the design of analog circuits for a desirable performance. Microelectron. J. 78: 54-62 (2018) - [j10]Reza Hashemian:
Amplifier Design for Specified Frequency Response Profiles Using Nullors-Hearing Aids, a Case Study. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4147-4156 (2018) - [c16]Reza Hashemian:
A Comprehensive Nodal/Branch Circuit Analysis Including Fixator-Norator Pairs in Analog Circuits. MWSCAS 2018: 125-128 - 2017
- [j9]Reza Hashemian, Mounika Vanga, Mahmoud Rahat:
Identifying and 3D Displaying Poles and Zeros in Analog Circuit Transfer Functions: Bode Surfaces. Circuits Syst. Signal Process. 36(6): 2473-2485 (2017) - [c15]Reza Hashemian:
Nullors in amplifier design for bandwidth using multiple feedbacks. CCECE 2017: 1-6 - 2016
- [j8]Reza Hashemian:
Finding poles and zeros in an analog circuit directly from its conductance matrix using eigenvalues. Comput. Electr. Eng. 56: 96-108 (2016) - [c14]Reza Hashemian:
Application of nullors in designing analog circuits for bandwidth. EIT 2016: 351-356 - [c13]Reza Hashemian:
RC and RL to LC circuit conversion, and its application in poles and zeros identification. ICECS 2016: 205-208 - 2015
- [c12]Reza Hashemian:
Identification and extraction of all real axis poles and zeros in RC and RL circuits. EIT 2015: 397-403 - [c11]Reza Hashemian:
S-plane bode plots - identifying poles and zeros in a circuit transfer function. LASCAS 2015: 1-4 - 2014
- [j7]Reza Hashemian:
Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 569-573 (2014) - [j6]Reza Hashemian:
Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 624-628 (2014) - [c10]Kamran Ravanasa, Reza Hashemian:
vLab, a high speed multi-accesses parallel processing remote laboratory access for FPGA design technology. EIT 2014: 377-381 - 2012
- [j5]Reza Hashemian:
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2220-2231 (2012) - 2010
- [j4]Reza Hashemian:
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs. VLSI Design 2010: 297083:1-297083:12 (2010)
2000 – 2009
- 2008
- [c9]Reza Hashemian:
Use of local biasing in designing analog integrated circuits. EIT 2008: 123-127 - 2007
- [c8]Reza Hashemian, Jason Riddley:
FPGA e-Lab, a Technique to Remote Access a Laboratory to Design and Test. MSE 2007: 139-140 - 2006
- [c7]Reza Hashemian:
Designing Analog Circuits with Reduced Biasing Power. ICECS 2006: 1069-1072 - 2004
- [j3]Reza Hashemian:
Condensed table of Huffman coding, a new approach to efficient decoding. IEEE Trans. Commun. 52(1): 6-8 (2004) - [c6]Reza Hashemian, Bipin Sreedharan:
A Hybrid Number System And Its Application In FPGA-DSP Technology. ITCC (2) 2004: 342-346 - 2003
- [c5]Reza Hashemian:
Direct Huffman Coding And Decoding Using The Table Of Code-Lengths. ITCC 2003: 237-
1990 – 1999
- 1995
- [j2]Reza Hashemian:
Memory efficient and high-speed search Huffman coding. IEEE Trans. Commun. 43(10): 2576-2581 (1995) - 1994
- [c4]Reza Hashemian:
Design of a 54-bit adder using a modified Manchester carry chain. Great Lakes Symposium on VLSI 1994: 204-207 - 1993
- [c3]Reza Hashemian:
High speed search and memory efficient Huffman coding. ISCAS 1993: 287-290 - 1992
- [c2]Reza Hashemian:
An alternative algorithm for high speed multiplication and addition using growing technique. Great Lakes Symposium on VLSI 1992: 124-129 - 1990
- [j1]Reza Hashemian:
Square Rooting Algorithms for Integer and Floatingg-Point Numbers. IEEE Trans. Computers 39(8): 1025-1029 (1990) - [c1]Reza Hashemian:
Parallel Addition Using Pipeline Structure. ICPP (1) 1990: 595-596
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