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ORCIDHans Eveking
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2010 – 2019
- 2011
[c23]Hans Eveking, Tobias Dornes, Martin Schweikert:
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. HLDVT 2011: 17-24- [c22]Tobias Dornes, Martin Schweikert, Hans Eveking:
Analyse von Gegenbeispielen bei Verifikation mit unvollständigen Eigenschaftssätzen. MBMV 2011: 123-132 - [c21]Martin Schweikert, Tobias Dornes, Hans Eveking:
Erzeugung von Operationseigenschaften aus UML Sequenzdiagrammen. MBMV 2011: 209-218 - 2010
- [c20]Tobias Dornes, Hans Eveking:
Formale Verifikation von Systemeigenschaften unter Verwendung normalisierter formaler Spezifikationen. MBMV 2010: 47-56 - [c19]Martin Schweikert, Hans Eveking:
Verwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen. MBMV 2010: 177-186
2000 – 2009
- 2009
- [c18]Martin Oberkönig, Martin Schickel, Hans Eveking:
Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften. MBMV 2009: 17-26 - 2008
- [c17]Martin Oberkönig, Martin Schickel, Hans Eveking:
Eine quantitative Vollständigkeitsanalyse für Eigenschaftssätze. MBMV 2008: 41-50 - 2007
- [c16]Martin Schickel, Martin Oberkönig, Martin Schweikert, Hans Eveking:
A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set. FDL 2007: 291-292 - [c15]Martin Oberkönig, Martin Schickel, Hans Eveking:
A Quantitative Completeness Analysis for Property-Sets. FMCAD 2007: 158-161 - [c14]Martin Braun, Minh D. Nguyen, Hans Eveking, Martin Schickel, Wolfgang Kunz:
Methoden zur Verifikation von Kommunikationsstrukturen. MBMV 2007: 223-232 - [c13]Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler:
Multi-Level Assertion-Based Design. MEMOCODE 2007: 85-86 - 2006
- [c12]Martin Schickel, Volker Nimbler, Martin Braun, Hans Eveking:
On Consistency and Completeness of Property-Sets. FDL 2006: 241-248 - [e3]Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak
, Vincent John Mooney III, Hans Eveking:
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. IFIP 200, Springer 2006, ISBN 978-0-387-33402-8 [contents] - 2003
- [e2]Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf:
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0 [contents] - 2001
- [j2]Hans Eveking:
Formale Verifikationsverfahren (Formal Verification). Informationstechnik Tech. Inform. 43(1): 5-7 (2001) - [c11]Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter:
Symbolic simulation techniques-state-of-the-art and applications. HLDVT 2001: 45-50 - 2000
- [c10]Claudia Blank, Gerd Ritter, Holger Hinrichsen, Hans Eveking:
Formale Verifikation der Register-Allokation. MBMV 2000: 27-35
1990 – 1999
- 1999
- [c9]Gerd Ritter, Holger Hinrichsen, Hans Eveking:
Formal Verification of Descriptions with Distinct Order of Memory Operations. ASIAN 1999: 308-321 - [c8]Gerd Ritter, Hans Eveking, Holger Hinrichsen:
Formal Verification of Designs with Complex Control by Symbolic Simulation. CHARME 1999: 234-249 - [c7]Hans Eveking, Holger Hinrichsen, Gerd Ritter:
Automatic Verification of Scheduling Results in High-Level Synthesis. DATE 1999: 59-64 - [c6]Holger Hinrichsen, Gerd Ritter, Hans Eveking:
Automatische Synthese und Verifikation von RISC-Prozessoren. MBMV 1999: 1-10 - 1995
- [e1]Paolo Camurati, Hans Eveking:
Correct Hardware Design and Verification Methods, IFIP WG 10.5 Advanced Research Working Conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995, Proceedings. Lecture Notes in Computer Science 987, Springer 1995, ISBN 3-540-60385-9 [contents] - 1994
- [c5]Hans Eveking:
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems. EURO-DAC 1994: 566-571 - 1993
- [c4]Hans Eveking, Stefan Höreth:
Optimization and Resynthesis of Complex Data-Paths. DAC 1993: 637-641 - 1991
- [b1]Hans Eveking:
Verifikation digitaler Systeme - eine Einführung in den Entwurf korrekter digitaler Systeme. Leitfäden und Monographien der Informatik, Teubner 1991, ISBN 978-3-519-02249-7, pp. I-XII, 1-308 - 1990
- [c3]Hans Eveking:
Automatic Verification of Extensions of Hardware Descriptions. CAV 1990: 2-12 - [c2]Hans Eveking:
Automatic Verification of Extensions of Hardware Descriptions. CAV (DIMACS/AMS volume) 1990: 3-14 - [c1]Hans Eveking, Christoph Mai:
Formal verification of timing conditions. EURO-DAC 1990: 512-517
1980 – 1989
- 1987
- [j1]Hans Eveking:
Formal reasoning about switch-level MOS descriptions. Microprocess. Microprogramming 21(1-5): 453-461 (1987)
Coauthor Index
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