ICCD 2005: San Jose, CA, USA

Cover

Introduction

Keynote Presentation

1.1 Power and Thermal Consideration in Processor Design (I)

1.2 Interconnect Prediction and Optimization

1.3 System-Level Architecture

Panel Discussion

2.1 Power aware System Design

2.2 Physical-Aware System-Level Analysis and Synthesis

2.3 SoC Test Methods

3.1 Reliable Circuit Design

3.2 High Level Systhesis

3.3 Verification of SoCs with Datapaths and Software

Keynote Address

4.1 Low Power Circuit Arhcitecture

4.2 Emerging Design Styles and Applications

4.3 Formal Verification - Form Hardware to Software (Invited)

5.1 Cache Memory Architecture

5.2 Gate Timing abd Power Analysis

5.3 Perform Modeling

6.1 Low Voltage Design

6.2 Physical-Aware Circuit Design

6.3 Verification and Test for Sequential Circuits and Delay Fault Models

7.1 New Memory Technologies (Invited)

8.1 High Performance Designs

8.2 Future VLSI Technologies and Their Impact

8.3 Architecture for Verifiability (Invited)

9.1 Low Power Circuit Architecture (II)

9.3 Formal Verification Methods

10.1 Power and Thermal Consideration in Processor Design (II)

10.2 Instruction Issue, Scheduling and Prediction

11.1 Circuit Consideration in Process Design

11.2 Logic Optimization