"High-Throughput Partially Parallel Inter-Chip Link Architecture for ..."

Naoya Onizawa et al. (2014)

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DOI: 10.1587/TRANSINF.E97.D.1546

access: closed

type: Journal Article

metadata version: 2020-04-11

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Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014)

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