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ISSCC 2021: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021. IEEE 2021, ISBN 978-1-7281-9549-0
- Laura Chizuko Fujino:
Reflections. 4 - Kenneth C. Smith, Laura Chizuko Fujino:
Remembrances of Dave Pricer. 5 - Makoto Ikeda:
Foreword Integrated Intelligence is the Future of Systems. 6 - Kevin Zhang, Makoto Ikeda:
Session 1 Overview Plenary Session - Invited Papers. 7-8 - Mark Liu:
1.1 Unleashing the Future of Innovation. 9-16 - Victor Peng:
Adaptive Intelligence in The New Computing Era. 17-21 - Dina Katabi:
1.3 Working at the Intersection of Machine Learning, Signal Processing, Sensors, and Circuits. 26-29 - Albert Theuwissen:
1.4 There's More to the Picture Than Meets the Eye*, and in the future it will only become more so. 30-35 - Theodoros Georgantas, Yves Baeyens, Alice Wang:
Session 2 Overview: Highlighted Chip Releases: 5G and Radar Systems Invited Papers. 36-37 - Ahmed Khalil, Islam A. Eshrah, Amr Elsherief, Ahmed Hesham Mehana, Mohamed Abdalla, Mohamed Mobarak, John Kilpatrick, Brian Hall, Ahmed Ashry, Hossam Fahmy, Sherif Salim, Russell Kernan, Brian Herdeg, Gary Sapia, Mohamed El-Nozahi, Mohamed Weheiba, Mark D'Amato, Christian Bautista, Kasey Chatzopoulos, Ahmed Ghoniem
, Yossif Mosa, Daniel Roll, Kerem Ok:
2.1 mm-Wave 5G Radios: Baseband to Waves. 38-40 - Krishnanshu Dandu, Sreekiran Samala, Karan Bhatia, Meysam Moallem, Karthik Subburaj, Zeshan Ahmad, Daniel Breen, Sunhwan Jang, Tim Davis, Mayank Singh, Shankar Ram, Vashishth Dudhia, Marc DeWilde, Dheeraj Shetty, John Samuel, Zahir Parkar, Cathy Chi, Pilar Loya, Zachary Crawford, John Herrington, Ross Kulak, Abhinav Daga, Rakesh Raavi, Ravi Teja, Rajesh Veettil, Daniel Khemraj, Indu Prathapan, Prakash Narayanan, Naveen Narayanan, Sangamesh Anandwade, Jasbir Singh, Venkatesh Srinivasan, Neeraj Nayak, Karthik Ramasubramanian, Brian P. Ginsburg
, Vijay Rentala:
High-Performance and Small Form-Factor mm-Wave CMOS Radars for Automotive and Industrial Sensing in 76-to-81GHz and 57-to-64GHz Bands. 39-41 - Saverio Trotta, Dave Weber, Reinhard W. Jungmaier, Ashutosh Baheti, Jaime Lien, Dennis Noppeney, Maryam Tabesh, Christoph Rumpler, Michael Aichner, Siegfried Albel, Jagjit S. Bal, Ivan Poupyrev:
SOLI: A Tiny Device for a New Human Machine Interface. 42-44 - Thomas Burd, Rangharajan Venkatesan, Dennis Sylvester:
Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers. 44-45 - Paul Paternoster, Andy Maki, Andres Hernandez, Mark Grossman, Michael Lau, David Sutherland, Aditya Mathad:
XBOX Series X: A Next-Generation Gaming Console SoC. 46-48 - Jack Choquette, Ming-Ju Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany:
3.2 The A100 Datacenter GPU and Ampere Architecture. 48-50 - Jian Ouyang, Xueliang Du
, Yin Ma, Jiaqiang Liu:
Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads. 50-51 - Sanu Mathew, Shidhartha Das, Hugh Mair:
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. 52-53 - HsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang:
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. 54-56 - Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei:
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. 56-58 - Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic
:
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. 58-60 - Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. 60-62 - Jiahao Liu, Zhen Zhu
, Yong Zhou, Ning Wang, Guanghai Dai, Qingsong Liu, Jianbiao Xiao
, Yuxiang Xie, Zirui Zhong, Hongduo Liu, Liang Chang, Jun Zhou:
4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring. 62-64 - Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka:
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. 64-66 - Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images. 66-68 - Tae Sung Kim, Seokhyun Lee, Kyungkoo Lee, Sunyoung Shin, SeungSick Jun, YongMi Lee, Seungyong Lee, Homin Kang, Changhyun Yim, Yohan Lim, Eikyung Moon, Sukhwan Lim, Kyung-Ah Jeong, Inyup Kang:
4.8 An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process. 68-70 - Jens Anders, Taeik Kim, David T. Blaauw:
Session 5 Overview: Analog Interfaces Analog Subcommittee. 70-71 - Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang:
5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. 72-74 - Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation. 74-76 - Jan A. Angevare, Youngcheol Chae, Kofi A. A. Makinwa:
A Highly Digital 2210μm2 Resistor-Based Temperature Sensor with a 1-Point Trimmed Inaccuracy of ± 1.3 ° C (3 σ) from -55 ° C to 125 ° C in 65nm CMOS. 76-78 - Sining Pan, Jan A. Angevare, Kofi A. A. Makinwa:
5.4 A Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor with a Self-Calibrated Inaccuracy of ±0.25° C(3 Σ) from -55°C to 125°C. 78-80 - Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan:
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing. 80-82 - Amirhossein Jouyaeian, Qinwen Fan, Mario Motz, Udo Ausserlechner, Kofi A. A. Makinwa:
A 25A Hybrid Magnetic Current Sensor with 64mA Resolution, 1.8MHz Bandwidth, and a Gain Drift Compensation Scheme. 82-84 - Arthur Campos de Oliveira, Jarno Groenesteijn, Remco J. Wiegerink, Kofi A. A. Makinwa:
5.7 A MEMS Coriolis Mass Flow Sensor with 300 μ g/h/√Hz Resolution and ± 0.8mg/h Zero Stability. 84-86 - Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim
:
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. 86-88 - Yiwu Tang, Yuan-Hung Chung, Sudhakar Pamarti
:
Session 6 Overview: High-Performance Receivers and Transmitters for Sub-6GHz Radios Wireless Subcommittee. 88-89 - Jongsoo Lee, Byoungjoong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee, Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Woniun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungiun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1. 90-92 - Mohammadreza Beikmirza, Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Dieuwert P. N. Mul, Leo C. N. de Vreede, Morteza S. Alavi
:
6.2 A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power Back-Off Operating in the 5GHz Band. 92-94 - Shi Bu, Sudhakar Pamarti
:
6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation. 94-96 - Jitesh Poojary
, Ramesh Harjani:
6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB. 96-98 - Mohammad Ali Montazerolghaem, Sergio Pires, Leo C. N. de Vreede, Masoud Babaie:
6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications. 98-100 - Xiaomin Li, Yibo Xu
, Lizheng Ren, Weiwei Ge, Jianlong Cai, Xinning Liu, Jun Yang:
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. 100-102 - Aravind Nagulu, Sasank Garikapati, Mostafa Essawy
, Igor Kadota
, Tingjun Chen, Arun Natarajan, Gil Zussman, Harish Krishnaswamy:
6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling. 100-102 - Kaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang:
A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End. 102-104 - Vyshnavi Suntharalingam, Calvin Yi-Ping Chao, Bruce Rae:
Session 7 Overview: Imagers and Range Sensors Imagers, Medical, Mems and Displays Subcommittee. 104-105 - Min-Sun Keel, Daeyun Kim, Yeomyung Kim, Myunghan Bae, Myoungoh Ki, Bumsik Chung, Sooho Son, Hoyong Lee, Heeyoung Jo, Seung-Chul Shin
, Sunjoo Hong, Jaeil An, Yonghun Kwon, Sungyoung Seo, Sunghyuck Cho, Youngchan Kim, Young-Gu Jin, Youngsun Oh, Yitae Kim, JungChak Ahn, Kyoungmin Koh, Yongin Park:
A 4-tap 3.5 μm 1.2 Mpixel Indirect Time-of-Flight CMOS Image Sensor with Peak Current Mitigation and Multi-User Interference Cancellation. 106-108 - Bumjun Kim, Seonghyeok Park
, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim:
7.2 A 48 ×4013.5 mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter. 108-110 - Oichi Kumagai, Junichi Ohmachi, Masao Matsumura, Shinichiro Yagi, Kenichi Tayu, Keitaro Amagawa, Tomohiro Matsukawa, Osamu Ozawa, Daisuke Hirono, Yasuhiro Shinozuka, Ryutaro Homma, Kumiko Mahara, Toshio Ohyama, Yousuke Morita, Shohei Shimada, Takahisa Ueno, Akira Matsumoto, Yusuke Otake, Toshifumi Wakano, Takashi Izawa:
A 189x600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems. 110-112 - Preethi Padmanabhan, Chao Zhang, Marco Cazzaniga, Baris Efe, Augusto Ronchini Ximenes, Myung-Jae Lee, Edoardo Charbon:
7.4 A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background Light. 111-113 - Jun Ogi, Takafumi Takatsuka, Kazuki Hizu, Yutaka Inaoka, Hongbo Zhu, Yasuhisa Tochigi, Yoshiaki Tashiro, Fumiaki Sano, Yusuke Murakawa, Makoto Nakamura, Yusuke Oike:
7.5 A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact Suppression. 113-115 - Chihiro Okada, Koushi Uemura, Luong Hung, Kouji Matsuura, Takashi Moue, Daisuke Yamazaki, Kazutoshi Kodama, Masafumi Okano, Takafumi Morikawa, Kazuyoshi Yamashita, Osamu Oka, Itai Shvartz, Golan Zeituni, Ariel Benshem, Noam Eshel, Yoshiaki Inada:
7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC. 116-118 - Martin Lefebvre
, Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. 118-120 - Tomoki Hirata, Hironobu Murata, Hideaki Matsuda, Yojiro Tezuka, Shiro Tsunai
:
7.8 A 1-inch 17Mpixel 1000fps Block-Controlled Coded-Exposure Back-Illuminated Stacked CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control. 120-122 - Jongeun Park, Sungbong Park, Kwansik Cho, Taehun Lee, Changkyu Lee, Donghyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, Dongmo Im, Haeyong Park, Jinyoung Kim, Jungho Cha, Tae-Hoon Kim, Insung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Park, Euiyeol Kim, Howoo Park, Jaekyu Lee, Yitae Kim, JungChak Ahn, Youngki Chung, ChungSam Jun, Hyunchul Kim, Chang-Rok Moon, Ho-Kyu Kang:
7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench Isolation. 122-124 - Yohan Frans, Patrick Yue, Thomas Toifl:
Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee. 124-125 - Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali
, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, Frank O'Mahony:
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. 126-128 - Minsoo Choi, Zhongkai Wang, Kyoungtae Lee
, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon:
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. 128-130 - Marcel A. Kossel, Vishal Khatri, Matthias Braendli
, Pier Andrea Francese
, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox:
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS. 130-132 - Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto:
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. 132-134 - Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan:
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. 134-136 - R. L. Nguyen, A. M. Castrillon, A. Fan, A. Mellati, Benjamín T. Reyes, Cindra Abidin, E. Olsen, F. Ahmad, Geoff Hatcher, J. Chana, Laura Biolato, L. Tse, L. Wang, M. Azarmnia, M. Davoodi, N. Campos, N. Fan, P. Prabha, Q. Lu, S. Cyrusian, S. Dallaire, S. Ho, S. Jantzi, T. Dusatko, W. Elsharkasy:
8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET. 136-138 - P. Mishra, A. Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, M. Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou:
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. 138-140 - James Bailey
, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan:
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. 140-142 - Sukhwan Lim, Luca Benini, Vivienne Sze:
Session 9 Overview: ML Processors From Cloud to Edge Machine Learning Subcommittee. 142-143 - Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim
, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun
, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. 144-146 - Huiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li
, Shouyi Yin, Shaojun Wei, Leibo Liu:
9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. 146-148 - Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon:
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree. 148-150 - Nimish Shah
, Laura Isabel Galindez Olascoaga, Shirui Zhao
, Wannes Meert
, Marian Verhelst
:
9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm. 150-152 - Jun-Seok Park, Jun-Woo Jang, Heonsoo Lee, Dongwoo Lee
, Sehwan Lee, Hanwoong Jung, Seungwon Lee, Suknam Kwon, Kyung-Ah Jeong, Joon-Ho Song, Sukhwan Lim, Inyup Kang:
9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC. 152-154 - Ryoji Eki, Satoshi Yamada, Hiroyuki Ozawa, Hitoshi Kai, Kazuyuki Okuike, Hareesh Gowtham, Hidetomo Nakanishi, Edan Almog, Yoel Livne, Gadi Yuval, Eli Zyss, Takashi Izawa:
9.6 A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor. 154-156 - Yuncheng Lu, Van Loi Le, Tony Tae-Hyoung Kim:
9.7 A 184 µ W Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices. 156-158 - Thierry Tambe
, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush
, David Brooks, Gu-Yeon Wei:
9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET. 158-160 - Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar
, Mingoo Seok:
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device. 160-162 - Seyfi S. Bazarjani, Jongwoo Lee, Marco Corsi:
Session 10 Overview: Continuous-Time ADCs and DACs Data Converter Subcommittee. 162-163 - Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang, Jaehoon Lee, Moo-Yeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee:
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter. 164-166 - Somok Mondal
, Omid Ghadami
, Drew A. Hall
:
10.2 A 139 µ W 104.8dB-DR 24 kHz-BW CT ΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs. 166-168 - Lu Jie
, Hsiang-Wen Chen
, Boyi Zheng, Michael P. Flynn:
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. 167-169 - Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun:
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. 170-172 - Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin:
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. 172-174 - Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet:
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. 174-176 - Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet:
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. 176-178 - Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany:
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. 178-179 - Ramy Yousry, Ehung Chen, Yu-Ming Ying, Mohammed Abdullatif, Mohammad Elbadry, Ahmed ElShater, Tsz-Bin Liu, Joonyeong Lee, Dhinessh Ramachandran, Kaiz Wang, Chih-Hao Weng, Mau-Lin Wu, Tamer A. Ali:
11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology. 180-182 - Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren:
11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. 181-183 - Kelvin McCollough, Scott D. Huss, James Vandersand, Randall Smith, Chris Moscone, Qazi Omar Farooq:
A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications. 184-185 - Zhaowen Wang
, Yudong Zhang, Yuka Onizuka, Peter R. Kinget:
11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links. 186-188 - Dongseok Shin, Hyung Seok Kim, Chuanchang Liu, Priya Wali
, Savyasaachi Keshava Murthy, Yongping Fan:
11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET. 188-190 - Hao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James E. Jaussi:
11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS. 190-192 - Atharav Atharav, Behzad Razavi:
11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS. 192-194 - Ramin Farjadrad, Kambiz Kaviani, David Nguyen, Michael Brown, Govert Geelen, Corné Bastiaansen, Narendra Rao, Viswa Popuri, Greg Shen, Hamid Khatibi, Saudas Dey, Anirban Chatterjee, David Shen, Peter Zijlstra, Harrie Gunnink, Kebin Zhang, Venkat Penumuchu, Oliver Weiss, Edward J. F. Paulus, Joost Briaire:
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS. 194-196 - Jack W. Holloway, Georgios C. Dogiamis
, Ruonan Han:
A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler. 196-198 - Sriram R. Vangal, Long Yan, Frederic Gianesello:
Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee. 198-199 - Miao Meng
, Manideep Dunna, Hans Chinghan Yu, Shihkai Kuo, Po-Han Peter Wang
, Dinesh Bharadia, Patrick P. Mercier
:
12.2 Improving the Range of WiFi Backscatter Via a Passive Retro-Reflective Single-Side-Band-Modulating MIMO Array and Non-Absorbing Termination. 202-204 - Qiang Zhou
, Yan He, Kaiyuan Yang
, Taiyun Chi:
12.3 Exploring PUF-Controlled PA Spectral Regrowth for Physical-Layer Identification of IoT Nodes. 204-206 - Denis Daly, Shawn S. H. Hsu, Edoardo Charbon:
Session 13 Overview: Cryo-CMOS for Quantum Computing Technology Directions Subcommittee. 206-207 - Jong Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano:
A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. 208-210 - Andrea Ruffino
, Yatao Peng, Tsung-Yeh Yang, John Michniewicz
, Miguel Fernando Gonzalez-Zalba
, Edoardo Charbon:
A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots. 210-212 - Bagas Prabowo
, Guoji Zheng, Mohammadreza Mehrpoo, Bishnu Patra
, Patrick Harvey-Collard
, Jurgen Dijkema, Amir Sammak, Giordano Scappucci
, Edoardo Charbon, Fabio Sebastiano, Lieven M. K. Vandersypen, Masoud Babaie:
A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology. 212-214 - Gerd Kiene, Alessandro Catania, Ramon Overwater
, Paolo Bruschi, Edoardo Charbon, Masoud Babaie, Fabio Sebastiano:
13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS. 214-216 - Bodhisatwa Sadhu, Matteo Bassi, Vito Giannini:
Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless Subcommittee. 216-217