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ORCID"A 40-nm low-power SRAM with multi-stage replica-bitline technique for ..."
Shigenobu Komatsu et al. (2009)
- Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704
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