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"65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic ..."

Masanao Yamaoka et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523218

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC 2008: 384-385

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