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ORCIDReConFig 2018: Cancun, Mexico
- David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt:
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018. IEEE 2018, ISBN 978-1-7281-1968-7 - Safdar Mahmood, Pavel Shydlouski, Michael Hübner:
An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse Kinematics. 1-6 - Daniel Ziener
, Jutta Pirkl, Jürgen Teich:
Configuration Tampering of BRAM-based AES Implementations on FPGAs. 1-7 - Zheming Jin, Hal Finkel:
Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC Kernel. 1-6 - Paul Sathre, Ahmed E. Helal, Wu-chun Feng:
A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and Transformation. 1-8 - Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapotre, Guy Gogniat:
A small and adaptive coprocessor for information flow tracking in ARM SoCs. 1-8 - Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman:
LaKe: The Power of In-Network Computing. 1-8 - Dillon Huff, Pat Hanrahan:
Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures. 1-6 - Mohamed W. Hassan, Ahmed E. Helal, Peter M. Athanas, Wu-Chun Feng, Yasser Y. Hanafy:
Exploring FPGA-specific Optimizations for Irregular OpenCL Applications. 1-8 - Hsin-Yu Ting, Ardalan Amiri Sani, Eli Bozorgzadeh:
System Services for Reconfigurable Hardware Acceleration in Mobile Devices. 1-6 - Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao:
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. 1-8 - Ali Jafari, Morteza Hosseini, Houman Homayoun, Tinoosh Mohsenin:
A Scalable and Low Power DCNN for Multimodal Data Classification. 1-6 - Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. 1-8 - Gökhan Akgün, Habib ul Hasan Khan, Mahmoud Ahmed Elshimy, Diana Göhringer:
Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loop. 1-8 - Tiziana Fanni, Alfonso Rodríguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre:
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. 1-8 - Lester Kalms, Hassan Ibrahim, Diana Göhringer:
Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAK. 1-6 - William L. Harrison, Gerard Allwein:
Language Abstractions for Hardware-based Control-Flow Integrity Monitoring. 1-6 - William Kamp, Norbert Abel, Gianni Comoretto:
Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators. 1-6 - Vladimir Estivill-Castro, René Hexel, Morgan McColl:
High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAs. 1-8 - Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. 1-6 - Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka:
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. 1-8 - Alan Ehret, Mihailo Isakov, Michel A. Kinsy:
Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration. 1-6 - Weiyi Sun, Hanqing Zeng, Yi-Hua Edward Yang, Viktor K. Prasanna:
Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGA. 1-8 - Philipp S. Käsgen, Markus Weinhardt, Christian Hochberger:
A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications. 1-4 - John McGlone, Paolo Palazzari, J. B. Leclere:
Accelerating Key In-memory Database Functionality with FPGA Technology. 1-8 - Kris Heid, Christian Hochberger:
AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCs. 1-7 - Arpit Soni, Yoon Kah Leow, Ali Akoglu:
Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures. 1-8 - Joe Avey, Phillip H. Jones, Joseph Zambreno:
An FPGA-based Hardware Accelerator for Iris Segmentation. 1-8 - Paulina Fusiara, Gijs Schoonderbeek, Johan Pragt, Leon Hiemstra, Sjouke Kuindersma, Menno Schuil, Grant Hampson:
Design and Fabrication of Full Board Direct Liquid Cooling Heat Sink for Densely Packed FPGA Processing Boards. 1-8 - Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso:
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. 1-6 - Zoya Dyka, Dan Kreiser, Ievgen Kabin, Peter Langendörfer:
Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCA. 1-6 - Kalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan:
Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs. 1-8 - Ievgen Kabin, Dan Kreiser, Zoya Dyka, Peter Langendörfer:
FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA. 1-7 - Ahmed Ferozpuri, Kris Gaj:
High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme. 1-8 - Ahmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet:
An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs. 1-6 - Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. 1-8 - Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision. 1-6 - Matthew Cauwels, Joseph Zambreno, Phillip H. Jones:
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. 1-8 - Sourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel:
A Highly Parallel FPGA Implementation of Sparse Neural Network Training. 1-4 - Michael Tempelmeier, Georg Sigl, Jens-Peter Kaps:
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. 1-6
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