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ORCIDIEEE Journal of Solid-State Circuits, Volume 49
Volume 49, Number 1, January 2014
- Michael P. Flynn:
New Associate Editor. 3 - Timothy C. Fischer, Byeong-Gyu Nam
, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs:
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. 4-8 - James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. 9-18 - Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. 19-31 - Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada:
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server. 32-40 - Weiwu Hu, Liang Yang, Bao-Xia Fan, Huandong Wang, Yunji Chen:
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS. 41-49 - Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. 50-60 - Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. 61-72 - Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa:
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. 73-83 - Paul N. Whatmough, Shidhartha Das, David M. Bull:
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. 84-94 - Sudhanshu Khanna, Steven Bartling, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams:
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications. 95-106 - Mahmut E. Sinangil, Anantha P. Chandrakasan:
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access. 107-117 - Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. 118-126 - Michael Bucher, Ravi T. Kollipara, Bruce Su, Liji Gopalakrishnan, Kashinath Prabhu, Pravin Kumar Venkatesan, Kambiz Kaviani, Barry Daly, William F. Stonecypher, Wayne D. Dettloff, Teva Stone, Fred Heaton, Yi Lu, Chris J. Madden, Sanath Bangalore, John C. Eble, Nhat Nguyen, Lei Luo:
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. 127-139 - Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli:
A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology. 140-153 - Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. 154-166 - Kiseok Song, Unsoo Ha, Jaehyuk Lee, Kyeongryeol Bong, Hoi-Jun Yoo:
An 87-mA · min Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System. 167-178 - Yuki Maruyama, Jordana Blacksberg, Edoardo Charbon:
A 1024 × 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS. 179-189 - Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. 190-201 - Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems. 202-211 - David Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles Alix Manier, Hermann Oppermann, Tommi Suni, James Dekker, Giorgio Allegato:
A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-µW RTC Mode and Programmable HF Clocks. 212-222 - Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. 223-231 - Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu:
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. 232-247 - Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen:
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe. 248-261 - Vladimir P. Petkov, Ganesh K. Balachandran, Jochen Beintner:
A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control. 262-270 - Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott:
A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor. 271-288 - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging. 289-300 - Leo Huf Campos Braga, Leonardo Gasparini, Lindsay Grant, Robert K. Henderson, Nicola Massari, Matteo Perenzoni, David Stoppa, Richard Walker:
A Fully Digital 8 × 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output. 301-314 - Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami:
A 0.18-µm CMOS SoC for a 100-m-Range 10-Frame/s 200 × 96-Pixel Time-of-Flight Depth Sensor. 315-330
Volume 49, Number 2, February 2014
- Giuseppe Papotto, Francesco Carrara, Alessandro Finocchiaro, Giuseppe Palmisano:
A 90-nm CMOS 5-Mbps Crystal-Less RF-Powered Transceiver for Wireless Sensor Network Nodes. 335-346 - Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-fu Lin, Wei Meng Lim:
A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology. 347-359 - Ahmad Mirzaei, Hooman Darabi:
Mutual Pulling Between Two Oscillators. 360-372 - Akshay Visweswaran, Robert Bogdan Staszewski, John R. Long:
A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting. 373-383 - Aliakbar Homayoun, Behzad Razavi:
Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise. 384-391 - John G. Kauffman, Pascal Witte, Matthias Lehmann, Joachim Becker, Yiannos Manoli, Maurits Ortmanns:
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW. 392-404 - Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. 405-415 - Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. 416-425 - Daibashish Gangopadhyay, Emily G. Allstot, Anna M. R. Dixon, Karthik Natarajan, Subhanshu Gupta, David J. Allstot:
Compressed Sensing Analog Front-End for Bio-Sensor Applications. 426-438 - Amir Borna, Khalil Najafi:
A Low Power Light Weight Wireless Multichannel Microsystem for Reliable Neural Recording. 439-451 - Ahmed Awny, Lothar Moeller, Joseph Junio, Christoph Scheytt, Andreas Thiede:
Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. 452-470 - Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. 471-485 - Chang-Joon Park, Marvin Onabajo, José Silva-Martínez:
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. 486-501 - Tae-Hwang Kong, Sung-Wan Hong, Gyu-Hyeong Cho:
A 0.791 mm2 On-Chip Self-Aligned Comparator Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump. 502-512 - Yingzhe Hu, Warren Rieutort-Louis, Josue Sanz-Robinson, Liechao Huang, Branko Glisic, James C. Sturm, Sigurd Wagner, Naveen Verma:
Large-Scale Sensing System Combining Large-Area Electronics and CMOS ICs for Structural-Health Monitoring. 513-523 - Daniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore:
Positive-Feedback Level Shifter Logic for Large-Area Electronics. 524-535 - Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. 536-544 - Kyle Craig, Yousef Shakhsheer, Saad Arrabi, Sudhanshu Khanna, John C. Lach, Benton H. Calhoun:
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance. 545-552
Volume 49, Number 3, March 2014
- Michael P. Flynn:
New Associate Editor. 563 - Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation. 564-580 - Baradwaj Vigraham, Peter R. Kinget:
A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation. 581-594 - Saqib Subhan, Eric A. M. Klumperink, Amir Ghaffari, Gerard J. M. Wienk, Bram Nauta:
A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics. 595-607 - Youngchang Yoon, Hyoungsoo Kim, Hyungwook Kim, Kun-Seok Lee, Chang-Ho Lee, James S. Kenney:
A 2.4-GHz CMOS Power Amplifier With an Integrated Antenna Impedance Mismatch Correction System. 608-621 - Mark Stoopman, Shady Keyrouz, Hubregt J. Visser, Kathleen Philips, Wouter A. Serdijn:
Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters. 622-634 - Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello:
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. 635-645 - Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello:
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. 646-656 - Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. 657-672 - Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. 673-682 - Jayanth Kuppambatti, Peter R. Kinget:
Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs. 683-694 - Seung-Chul Lee, Yun Chiu:
A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR. 695-707 - Wei-Te Lin, Hung-Yi Huang, Tai-Haur Kuo:
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique. 708-717 - Adrian Colli-Menchi, Joselyn Torres, Edgar Sánchez-Sinencio:
A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers. 718-728 - Jingxue Lu, Hyejeong Song, Ranjit Gharpurey:
A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator. 729-739 - Wei-Chung Chen, Su-Yi Ping, Tzu-Chi Huang, Yu-Huei Lee, Ke-Horng Chen, Chin-Long Wey:
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique. 740-750 - Nhan Tran, Shun Bai, Jiawei Yang, Hosung Chun, Omid Kavehei, Yuanyuan Yang, Vijay Muktamath, David C. Ng, Hamish Meffin, Mark E. Halpern, Efstratios Skafidas:
A Complete 256-Electrode Retinal Prosthesis Chip. 751-765 - Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs. 766-782 - Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. 783-794
Volume 49, Number 4, April 2014
- Hideyuki Kabuo, Jeffrey C. Gealow:
Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits. 799-800 - Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee:
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. 801-811 - David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack:
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. 812-826 - Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto:
A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder. 827-837 - Yingzhe Hu, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Naveen Verma:
A Self-Powered System for Large-Scale Strain Sensing by Combining CMOS ICs With Large-Area Electronics. 838-850 - Yu-Jie Huang, Te-Hsuen Tzeng, Tzu-Wei Lin, Che-Wei Huang, Pei-Wen Yen, Po-Hung Kuo, Chih-Ting Lin, Shey-Shi Lu:
A Self-Powered CMOS Reconfigurable Multi-Sensor SoC for Biomedical Applications. 851-866 - Ryan M. Field, Simeon Realov, Kenneth L. Shepard:
A 100 fps, Time-Correlated Single-Photon-Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS. 867-880 - Bardia Bozorgzadeh, Daniel P. Covey, Christopher D. Howard, Paul A. Garris, Pedram Mohseni:
A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pA rms , 400 V/s FSCV Sensing. 881-895 - Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang:
1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. 896-907 - Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih:
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. 908-916 - Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. 917-927 - Karthik Kadirvel, John Carpenter, Phuong Huynh, John Michael Ross, Robert Shoemaker, Brian Lum-Shue-Chan:
A Stackable, 6-Cell, Li-Ion, Battery Management IC for Electric Vehicles With 13, 12-bit ΣΔ ADCs, Cell Balancing, and Direct-Connect Current-Mode Communications. 928-934 - Shiuh-Hua Wood Chiang, Hyuk Sun, Behzad Razavi:
A 10-Bit 800-MHz 19-mW CMOS ADC. 935-949 - Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu:
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. 950-960 - Taehwan Oh, Hariprasath Venkatram, Un-Ku Moon:
A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. 961-971 - Ahmad Mirzaei, Mohyee Mikhemar, David Murphy, Hooman Darabi:
A 2 dB NF Receiver With 10 mA Battery Current Suitable for Coexistence Applications. 972-983 - Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun:
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS. 984-995 - Serkan Sayilir, Wing-Fai Loke, Jangjoon Lee, Harry Diamond, Benjamin R. Epstein, David L. Rhodes, Byunghoo Jung:
A -90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks. 996-1006 - KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. 1007-1016 - Bongjin Kim, Weichao Xu, Chris H. Kim:
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. 1017-1026 - Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman:
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. 1027-1035 - Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. 1036-1047 - Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe:
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface. 1048-1062 - Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta:
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. 1063-1074
Volume 49, Number 5, May 2014
- Waleed Khalil:
Introduction to the Special Section on the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. 1079-1080 - Wanghua Wu, Robert Bogdan Staszewski, John R. Long:
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. 1081-1096 - Run Chen, Hossein Hashemi:
A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing. 1097-1111 - Dlovan H. Mahrof, Eric A. M. Klumperink, Zhiyu Ru, Mark S. Oude Alink, Bram Nauta:
Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity. 1112-1124 - Piljae Park, Sungdo Kim, Sungchul Woo, Cheonsoo Kim:
A Centimeter Resolution, 10 m Range CMOS Impulse Radio Radar for Human Motion Monitoring. 1125-1134 - Xiongchuan Huang, Pieter Harpe, Guido Dolmans, Harmke de Groot, John R. Long:
A 780-950 MHz, 64-146 µW Power-Scalable Synchronized-Switching OOK Receiver for Wireless Event-Driven Applications. 1135-1147 - Amir Agah, Jefy Alex Jayamon, Peter M. Asbeck, Lawrence E. Larson, James F. Buckwalter:
Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS. 1148-1157 - Anna Moroni, Raffaella Genesi, Danilo Manstretta:
Analysis and Design of a 54 GHz Distributed "Hybrid" Wave Oscillator Array With Quadrature Outputs. 1158-1172 - Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. 1173-1183 - Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. 1184-1197 - Sedigheh Hashemi, Behzad Razavi:
Analysis of Metastability in Pipelined ADCs. 1198-1209 - Denis Guangyin Chen, Fang Tang, Man Kay Law, Amine Bermak:
A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor. 1210-1222 - Hamed Mazhab-Jafari, Karim Abdelhalim, Leyla Soleymani, Edward H. Sargent, Shana O. Kelley, Roman Genov:
Nanostructured CMOS Wireless Ultra-Wideband Label-Free PCR-Free DNA Analysis SoC. 1223-1241 - Yi Zhang, Dongsheng Ma:
A Fast-Response Hybrid SIMO Power Converter with Adaptive Current Compensation and Minimized Cross-Regulation. 1242-1255 - Vratislav Michal:
Absolute Value, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage. 1256-1270 - Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. 1271-1284
Volume 49, Number 6, June 2014
- Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, Kwyro Lee:
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization. 1286-1302 - Amir Ghaffari, Eric A. M. Klumperink, Frank E. van Vliet, Bram Nauta:
A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs. 1303-1316 - Francis Caster, Leland Gilreath, Shiji Pan, Zheng Wang, Filippo Capolino, Payam Heydari:
Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon. 1317-1332 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS. 1333-1344 - Lingli Xia, Jiao Cheng, Neil E. Glover, Patrick Chiang:
0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop. 1345-1355 - Nam-Sik Ryu, Seung Hyun Jang, Kwang Chun Lee, Yongchae Jeong:
CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application. 1356-1365 - Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. 1366-1382 - Jiayi Jin, Yang Gao, Edgar Sánchez-Sinencio:
An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure. 1383-1396 - Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis:
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors. 1397-1407 - Mohammad Sadegh Mehrjoo, James F. Buckwalter:
A 10 bit, 300 MS/s Nyquist Current-Steering Power DAC With 6 VPP Output Swing. 1408-1418 - Cheng Li, Rui Bai, Ayman Shafik, Ehsan Zhian Tabasy, Binhao Wang, Geng Tang, Chao Ma, Chin-Hui Chen, Zhen Peng, Marco Fiorentino, Raymond G. Beausoleil, Patrick Chiang, Samuel Palermo:
Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS. 1419-1436 - Dan Li, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti, Francesco Svelto:
A Low-Noise Design Technique for High-Speed CMOS Optical Receivers. 1437-1447
Volume 49, Number 7, July 2014
- Michael P. Flynn:
New Associate Editors. 1459 - Yann Deval, Stefan Rusu:
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC). 1460-1462 - Patrick P. Mercier, Saurav Bandyopadhyay, Andrew C. Lysaght, Konstantina M. Stankovic, Anantha P. Chandrakasan:
A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications. 1463-1474 - Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin:
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. 1475-1486 - Anh-Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. 1487-1498 - Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche:
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. 1499-1505 - Yang Guo, Christopher Aquino, David Zhang, Boris Murmann:
A Four-Channel, ±36 V, 780 kHz Piezo Driver Chip for Structural Health Monitoring. 1506-1513 - Haifeng Ma, Ronan A. R. van der Zee, Bram Nauta:
Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage. 1514-1524 - Junfeng Jiang, Wilko J. Kindt, Kofi A. A. Makinwa:
A Continuous-Time Ripple Reduction Technique for Spinning-Current Hall Sensors. 1525-1534 - Mattias Andersson, Martin Anderson, Lars Sundström, Sven Mattisson, Pietro Andreani:
A Filtering ΔΣ ADC for LTE and Beyond. 1535-1547 - Sebastian Zeller, Christian Muenker, Robert Weigel, Thomas Ussmueller:
A 0.039 mm2 Inverter-Based 1.82 mW 68.6~ dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques. 1548-1560 - Pierre Gasnier, Jérôme Willemin, Sebastien Boisseau, Ghislain Despesse, Cyril Condemine, Guillaume Gouvernet, Jean-Jacques Chaillout:
An Autonomous Piezoelectric Energy Harvesting IC Based on a Synchronous Multi-Shot Technique. 1561-1570 - Vlad Anghel, Christopher Bartholomeusz, Anca Gabriela Vasilica, Gheorghe Pristavu, Gheorghe Brezeanu:
Variable Off-Time Control Loop for Current-Mode Floating Buck Converters in LED Driving Applications. 1571-1579 - Tzu-Chi Huang, Ruei-Hong Peng, Tsu-Wei Tsai, Ke-Horng Chen, Chin-Long Wey:
Fast Charging and High Efficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics. 1580-1594 - Michael Peter Kennedy, Hongjia Mo, Brian Fitzgibbon, Austin Harney, Hyman Shanan, Mike Keaveney:
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller. 1595-1605 - Noël Deferm, Patrick Reynaert:
A 120 GHz Fully Integrated 10 Gb/s Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire Antenna in 45 nm Low Power CMOS. 1606-1616 - Wouter Steyaert, Patrick Reynaert:
A 0.54 THz Signal Generator in 40 nm Bulk CMOS With 22 GHz Tuning Range and Integrated Planar Antenna. 1617-1626 - Nicola Codega, Paolo Rossi, Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer. 1627-1638 - Charles Wu, Elad Alon, Borivoje Nikolic:
A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver. 1639-1652 - Stefan Shopov, Andreea Balteanu, Sorin P. Voinigescu:
A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters. 1653-1664
Volume 49, Number 8, August 2014
- Ken Suyama, Andrea Mazzanti:
Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference. 1667-1668 - Mehran Bakhshiani, Michael A. Suster, Pedram Mohseni:
A Broadband Sensor Interface IC for Miniaturized Dielectric Spectroscopy From MHz to GHz. 1669-1681 - Seokhyeon Jeong, Zhiyoong Foo, Yoonmyung Lee, Jae-Yoon Sim, David T. Blaauw, Dennis Sylvester:
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes. 1682-1693 - Ron Kapusta, Haiyang Zhu, Colin Lyden:
Sampling Circuits That Break the kT/C Thermal Noise Limit. 1694-1701 - Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Chengyue Yu, Maurice Tjie, Ahmet Tekin, Xicheng Jiang, Todd Brooks:
A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications. 1702-1714 - Manideep Gande, Hariprasath Venkatram, Ho-Young Lee, Jon Guerber, Un-Ku Moon:
Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling. 1715-1724 - Yida Duan, Elad Alon:
A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB. 1725-1738 - Sedigheh Hashemi, Behzad Razavi:
A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate. 1739-1750 - Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8 Bit 4 GS/s 120 mW CMOS ADC. 1751-1761 - Salvatore Levantino, Giovanni Marzin, Carlo Samori:
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs. 1762-1772 - Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. 1773-1784 - Alvin Li, Shiyuan Zheng, Jun Yin, Xun Luo, Howard C. Luong:
A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications. 1785-1799 - Naga Rajesh, Shanthi Pavan:
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming. 1800-1814 - Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx:
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. 1815-1826 - Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu:
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. 1827-1836 - Man Pun Chan, Philip K. T. Mok:
A Monolithic Digital Ripple-Based Adaptive-Off-Time DC-DC Converter With a Digital Inductor Current Sensor. 1837-1847 - Dongkyung Park, Zhidong Liu, Hoi Lee:
A 40 V 10 W 93%-Efficiency Current-Accuracy-Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications. 1848-1860 - Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. 1861-1871
Volume 49, Number 9, September 2014
- Albert Z. Wang:
Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. 1875 - Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright:
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. 1876-1885 - Philipp Ritter, Stéphane Le Tual, Bruno Allard, Michael Möller:
Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold. 1886-1894 - Quentin Beraud-Sudreau, Jean-Baptiste Bégueret, Olivier Mazouffre, Michel Pignol, Louis Baguena, Claude Neveu, Yann Deval, Thierry Taris:
SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link. 1895-1904 - Jianjun Yu, Feng Zhao, Joseph Cali, Fa Foster Dai, Desheng Ma, Xueyang Geng, Yuehai Jin, Yuan Yao, Xin Jin, J. David Irwin, Richard C. Jaeger:
An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology. 1905-1915 - Mohamed Elkhouly, Yanfei Mao, Chafik Meliani, Johann-Christoph Scheytt, Frank Ellinger:
A G-Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology. 1916-1926 - X. Shawn Wang, Xin Wang, Fei Lu, Chen Zhang, Zongyu Dong, Li Wang, Rui Ma, Zitao Shi, Albert Z. Wang, Mau-Chung Frank Chang, Dawn Wang, Alvin J. Joseph, C. Patrick Yue:
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection. 1927-1941 - Hadar Dagan, Aviv Shapira, Adam Teman, Anatoli Mordakhay, Samuel Jameson, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin, Eran Socher, Alexander Fish:
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory. 1942-1957 - Ahmad Mirzaei, Hooman Darabi:
Pulling Mitigation in Wireless Transmitters. 1958-1970 - Travis Forbes, Ranjit Gharpurey:
A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver. 1971-1983 - Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. 1984-1994 - Nachiket V. Desai, Jerald Yoo, Anantha P. Chandrakasan:
A Scalable, 2.9 mW, 1 Mb/s e-Textiles Body Area Network Transceiver With Remotely-Powered Nodes and Bi-Directional Data Communication. 1995-2004 - Jiawei Xu, Srinjoy Mitra, Akinori Matsumoto, Shrishail Patki, Chris Van Hoof, Kofi A. A. Makinwa, Refet Firat Yazicioglu:
A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks. 2005-2016 - Ethem Erkan Aktakka, Khalil Najafi:
A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes. 2017-2029 - Yi Zhao, Leonardo Vera, John R. Long:
A 10 Gb/s, 6 V p-p , Digitally Controlled, Differential Distributed Amplifier MZM Driver. 2030-2043 - Seung-Hun Lee, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
Current-Mode Transceiver for Silicon Interposer Channel. 2044-2053 - Inyong Kwon, Seongjong Kim, David Fick, Myungbo Kim, Yen-Po Chen, Dennis Sylvester:
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails. 2054-2066 - Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. 2067-2082 - P. V. Ananda Mohan, Eric A. M. Klumperink, Dlovan H. Mahrof, Bram Nauta:
Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity". 2083
Volume 49, Number 10, October 2014
- Michael P. Flynn:
New Associate Editor [Ken Suyama]. 2087 - Hyun-Chul Park, Saeid Daneshgar, Zach Griffith, Miguel Urteaga, Byung-Sung Kim, Mark J. W. Rodwell:
Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns. 2089-2102 - Andreea Balteanu, Stefan Shopov, Sorin P. Voinigescu:
A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation. 2103-2113 - Saeid Daneshgar, Zach Griffith, Munkyo Seo, Mark J. W. Rodwell:
Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers. 2114-2126 - Sushmit Goswami, Helen Kim, Joel L. Dawson:
A Frequency-Agile RF Frontend Architecture for Multi-Band TDD Applications. 2127-2140 - Woonyun Kim, Ki Seok Yang, Jeonghu Han, Jaejoon Chang, Chang-Ho Lee:
An EDGE/GSM Quad-Band CMOS Power Amplifier. 2141-2149 - Kunal Datta, Hossein Hashemi:
Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers. 2150-2171 - Ni Xu, Woogeun Rhee, Zhihua Wang:
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation. 2172-2186 - Radha S. Rajan, Shanthi Pavan:
Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering. 2187-2198 - Marco Crescentini, Marco Bennati, Marco Tartagni:
A High Resolution Interface for Kelvin Impedance Sensing. 2199-2212 - Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. 2213-2227 - Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu:
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. 2228-2242 - Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. 2243-2258 - Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. 2259-2276 - Dongwon Kwon, Gabriel A. Rincón-Mora:
A Single-Inductor 0.35 µm CMOS Energy-Investing Piezoelectric Harvester. 2277-2291 - Christos Vezyrtzis, Weiwei Jiang, Steven M. Nowick, Yannis P. Tsividis:
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate. 2292-2304 - Jun-Eun Park, Dong-Hyuk Lim, Deog-Kyoon Jeong:
A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels. 2305-2318 - Jihyun Cho, Jaehyuk Choi, Seong-Jin Kim, Seokjun Park, Jungsoon Shin, James D. K. Kim, Euisik Yoon:
A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution. 2319-2332 - Christian Brandli, Raphael Berner, Minhao Yang, Shih-Chii Liu, Tobi Delbrück:
A 240 × 180 130 dB 3 µs Latency Global Shutter Spatiotemporal Vision Sensor. 2333-2341 - Ruoyu Xu, Wai Chiu Ng, George Jie Yuan, Shouyi Yin, Shaojun Wei:
A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision. 2342-2351 - Chih-Wen Lu, Ping-Yeh Yin, Ying-Ting Lin:
A Column Driver Architecture With Double Time-Division Multiplexing RDACs for TFT-LCD Applications. 2352-2364
Volume 49, Number 11, November 2014
- Zhihua Wang:
Introduction to the Special Section on the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC). 2375-2376 - Xin Zhang, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS. 2377-2386 - Xicheng Jiang, Jungwoo Song, Darwin Cheung, Minsheng Wang, Sasi Kumar Arunachalam:
Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR. 2387-2396 - Chung-Yu Wu, Xin-Hong Qian, Ming-Seng Cheng, Yu-An Liang, Wei-Ming Chen:
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices. 2397-2407 - Xiayun Liu, Mehran M. Izad, Libin Yao, Chun-Huat Heng:
A 13 pJ/bit 900 MHz QPSK/16-QAM Band Shaped Transmitter Based on Injection Locking and Digital PA for Biomedical Applications. 2408-2421 - Xin Liu, Jun Zhou, Yongkui Yang, Bo Wang, Jingjing Lan, Chao Wang, Jianwen Luo, Wang Ling Goh, Tony Tae-Hyoung Kim, Minkyu Je:
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring. 2422-2434 - Chacko John Deepu, Xiaoyang Zhang, Wen-Sin Liew, David Liang Tai Wong, Yong Lian:
An ECG-on-Chip With 535 nW/Channel Integrated Lossless Data Compressor for Wireless Sensors. 2435-2448 - Wai Pan Chan, Margarita Narducci, Yuan Gao, Ming-Yuan Cheng, Jia Hao Cheong, Arup K. George, Daw Don Cheam, Siew Chong Leong, Maria Ramona B. Damalerio, Ruiqi Lim, Ming-Ling Tsai, Abdur R. A. Rahman, Mi Kyoung Park, Zhi-Hui Kong, Rao Jai Prashanth, Minkyu Je:
A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring. 2449-2461 - Laura Fick, David Fick, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS. 2462-2473 - Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli:
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. 2474-2489 - Pier Andrea Francese, Thomas Toifl, Peter Buchmann, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen:
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. 2490-2502 - Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura:
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver. 2503-2514 - Amrith Sukumaran, Shanthi Pavan:
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. 2515-2525 - Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka:
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving. 2526-2533 - Tony Tae-Hyoung Kim, Ngoc Le Ba:
Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C. 2534-2546 - Fujian Lin, Pui-In Mak, Rui Paulo Martins:
An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF. 2547-2559 - Ehsan Zhian Tabasy, Ayman Shafik, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications. 2560-2574 - Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski:
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter. 2575-2587 - Chintan Thakkar, Nathan Narevsky, Christopher D. Hull, Elad Alon:
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver. 2588-2607 - Linfei Guo, Tong Ge, Joseph Sylvester Chang:
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier. 2608-2617 - Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. 2618-2630 - Young-Hoon Song, Noah Hae-Woong Yang, Hao Li, Patrick Yin Chiang, Samuel Palermo:
An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning. 2631-2643 - Sai Zhang, Jane S. Tu, Naresh R. Shanbhag, Philip T. Krein:
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. 2644-2657 - Xiao Liang Tan, Sau Siong Chong, Pak Kwong Chan, Uday Dasgupta:
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load. 2658-2672 - Youngkook Ahn, Inho Jeon, Jeongjin Roh:
A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control. 2673-2683 - Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury:
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. 2684-2693 - Ying-Khai Teh, Philip K. T. Mok:
Design of Transformer-Based Boost Converter for High Internal Resistance Energy Harvesting Sources With 21 mV Self-Startup Voltage and 74% Power Efficiency. 2694-2704 - Marco Ballini, Jan Mueller, Paolo Livi, Yihui Chen, Urs Frey, Alexander Stettler, Amir Shadmani, Vijay Viswam, Ian Lloyd Jones, David Jackel, Milos Radivojevic, Marta K. Lewandowska, Wei Gong, Michele Fiscella, Douglas J. Bakkum, Flavio Heer, Andreas Hierlemann:
A 1024-Channel CMOS Microelectrode Array With 26, 400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro. 2705-2719 - Erik Ryman, Anders Emrich, Stefan Back Andersson, Lars J. Svensson, Per Larsson-Edefors:
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis. 2720-2729 - Yildiz Sinangil, Anantha P. Chandrakasan:
A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing. 2730-2739 - Rahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, Anantha P. Chandrakasan:
Correction to "Reconfigurable Processor for Energy-Efficient Computational Photography". 2740
Volume 49, Number 12, December 2014
- Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu:
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). 2743-2747 - Davide Bianchi, Giorgio Ferrari, Angelo Rottigni, Marco Sampietro:
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150 MHz With Sub-aF Resolution. 2748-2757 - Baradwaj Vigraham, Jayanth Kuppambatti, Peter R. Kinget:
Switched-Mode Operational Amplifiers and Their Application to Continuous-Time Filters in Nanoscale CMOS. 2758-2772 - Loai G. Salem, Patrick P. Mercier:
A Recursive Switched-Capacitor DC-DC Converter Achieving 2N-1 Ratios With High Efficiency Over a Wide Output Voltage Range. 2773-2787 - Lin Cheng, Yonggen Liu, Wing-Hung Ki:
A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator. 2788-2799 - Wanyeong Jung, Sechang Oh, Suyoung Bang, Yoonmyung Lee, Zhiyoong Foo, Gyouho Kim, Yiqun Zhang, Dennis Sylvester, David T. Blaauw:
An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler. 2800-2811 - Saurav Bandyopadhyay, Patrick P. Mercier, Andrew C. Lysaght, Konstantina M. Stankovic, Anantha P. Chandrakasan:
A 1.1 nW Energy-Harvesting System with 544 pW Quiescent Power for Next-Generation Implants. 2812-2824 - Frank M. Yaul, Anantha P. Chandrakasan:
A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation. 2825-2834 - Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult:
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. 2835-2845 - Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. 2846-2856 - Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop:
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration. 2857-2867 - Yunzhi Dong, William Yang, Richard Schreier, Ali Sheikholeslami, Sudhir Korrapati:
A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS. 2868-2877 - Daniel R. McMahill, Dwaine S. Hurta, Brian Brandt, Miaochen Wu, Paul Kalthoff, Geir S. Ostrem:
A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit DAC. 2878-2890 - Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI. 2891-2901 - Shouhei Kousai, Kohei Onizuka, Junji Wadatsumi, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier. 2902-2914 - Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. 2915-2924 - Vito Giannini, Davide Guermandi, Qixian Shi, Alaa Medra, Wim Van Thillo, André Bourdoux, Piet Wambacq:
A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS. 2925-2937 - Ullrich R. Pfeiffer, Yan Zhao, Janusz Grzyb, Richard Al Hadi, Neelanjan Sarmah, Wolfgang Forster, Holger Rücker, Bernd Heinemann:
A 0.53 THz Reconfigurable Source Module With Up to 1 mW Radiated Power for Diffuse Illumination in Terahertz Imaging Applications. 2938-2950 - Pei-Yuan Chiang, Zheng Wang, Omeed Momeni, Payam Heydari:
A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range. 2951-2963 - Wei-Sung Chang, Po-Chun Huang, Tai-Cheng Lee:
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector. 2964-2975 - Taegeun Yoo, Hong Chang Yeoh, Yun-Hwan Jung, Seong Jin Cho, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek:
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS. 2976-2989 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications. 2990-3004 - Yao-Hong Liu, Ao Ba, Johan H. C. van den Heuvel, Kathleen Philips, Guido Dolmans, Harmke de Groot:
A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF Phase-to-Digital Converter for Wireless Personal/Body Area Networks. 3005-3017 - Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan:
A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS. 3018-3030 - Michael Boers, Bagher Afshar, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bevin George Perumana, Theodoros Chalvatzis, Spyros Kavvadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Jesus A. Castaneda, Tirdad Sowlati, Maryam Rofougaran, Ahmadreza Rofougaran:
A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity. 3031-3045 - Jin Zhou, Anandaroop Chakrabarti, Peter R. Kinget, Harish Krishnaswamy:
Low-Noise Active Cancellation of Transmitter Leakage and Transmitter Noise in Broadband Wireless Receivers for FDD/Co-Existence. 3046-3062 - Joung Won Park, Behzad Razavi:
Channel Selection at RF Using Miller Bandpass Filters. 3063-3078 - Tawfiq Musah, James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Gokce Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper:
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. 3079-3090 - Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong:
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. 3091-3103 - Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong, Ratnakar Dadi, Arif Amin, Ahmed Ragab, Ming-Ju Edward Lee:
A 15-22 Gbps Serial Link in 28 nm CMOS With Direct DFE. 3104-3115 - Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. 3116-3129 - Enrico Mammei, Fabrizio Loi, Francesco Radice, Angelo Dati, Melchiorre Bruccoleri, Matteo Bassi, Andrea Mazzanti:
Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS. 3130-3140 - Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Derek Tam, Ichiro Fujimori:
A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS. 3141-3155
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