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2010 – 2019
- 2014
[j1]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong:
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 3091-3103 (2014)- [c3]Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri, Gordon Chan, Hairong Gao:
Shift register multi-phase clock based downsampled floating tap DFE for serial links. ISCAS 2014: 2469-2472 - [c2]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong:
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. ISSCC 2014: 38-39 - 2012
- [c1]Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri:
A class of downsampled floating tap DFE architectures with application to serial links. ISCAS 2012: 325-328
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