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Yasufumi Sakai
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2020 – today
- 2023
- [c15]Kengo Matsumoto, Tomoya Matsuda, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai:
A Mixed-Precision Quantization Method without Accuracy Degradation Using Semilayers. ACML 2023: 882-894 - [c14]Tomoya Matsuda, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi
, Yasufumi Sakai:
Semilayer-Wise Partial Quantization Without Accuracy Degradation or Back Propagation. ICANN (9) 2023: 283-295 - [c13]Yasufumi Sakai, Thang Dang, Shigeki Fukuta, Koichi Shirahata, Atsushi Ishikawa
, Atsuki Inoue, Hiroshi Kawaguchi, Árni Björn Höskuldsson, Egill Skúlason:
Self-Supervised Learning with Atom Replacement for Catalyst Energy Prediction by Graph Neural Networks. INNS DLIA@IJCNN 2023: 458-467 - 2022
- [c12]Thang Dang
, Yasufumi Sakai, Tsuguchika Tabaru, Akihiko Kasagi:
Regularizing Data for Improving Execution Time of NLP Model. FLAIRS 2022 - [c11]Kazuki Okado, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi
, Yasufumi Sakai:
Channel-wise quantization without accuracy degradation using Δloss analysis. ICMLT 2022: 56-61 - [c10]Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru, Atsuki Inoue, Hiroshi Kawaguchi
:
Automatic Pruning Rate Derivation for Structured Pruning of Deep Neural Networks. ICPR 2022: 2561-2567 - [c9]Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru:
Structured Pruning with Automatic Pruning Rate Derivation for Image Processing Neural Networks. ISMSI 2022: 100-104 - 2021
- [c8]Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai, Fuyuka Yamada:
Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization. ACML 2021: 886-901 - [c7]Akihiko Kasagi, Masahiro Asaoka, Akihiro Tabuchi, Yosuke Oyama, Takumi Honda, Yasufumi Sakai, Thang Dang
, Tsuguchika Tabaru:
Efficient and Large Scale Pre-training Techniques for Japanese Natural Language Processing. CANDAR 2021: 108-113 - [c6]Fuyuka Yamada, Satoki Tsuji, Hiroshi Kawaguchi
, Atsuki Inoue, Yasufumi Sakai
:
A High-Speed Neural Architecture Search Considering the Number of Weights. KI 2021: 109-115
2010 – 2019
- 2019
- [j2]Yasufumi Sakai
, Bruno U. Pedroni, Siddharth Joshi, Satoshi Tanabe, Abraham Akinin
, Gert Cauwenberghs
:
Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(4): 658-667 (2019) - [c5]Yasufumi Sakai, Bruno U. Pedroni, Siddharth Joshi, Abraham Akinin, Gert Cauwenberghs
:
DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity. AICAS 2019: 76-80 - [c4]Yukito Tsunoda, Takahiro Notsu, Yasufumi Sakai, Naoki Hamada, Toshihiko Mori, Teruo Ishihara, Atsuki Inoue:
Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design. GECCO (Companion) 2019: 405-406 - 2016
- [c3]Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC 2016: 64-65 - [c2]Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2014
- [j1]Kazuaki Oishi, Eiji Yoshida
, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. IEEE J. Solid State Circuits 49(12): 2915-2924 (2014) - [c1]Kazuaki Oishi, Eiji Yoshida
, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura
, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. ISSCC 2014: 60-61
Coauthor Index
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