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ORCIDFreeman Zhong
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2010 – 2019
- 2014
[j3]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong:
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 3091-3103 (2014)- [c5]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong:
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. ISSCC 2014: 38-39 - 2013
- [c4]Yikui Jen Dong, Freeman Zhong:
A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations. ISCAS 2013: 1400-1403 - 2011
- [j2]Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. IEEE J. Solid State Circuits 46(12): 3126-3139 (2011) - [c3]Shaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. ISSCC 2011: 348-350
2000 – 2009
- 2007
- [c2]Yikui Dong, Cathy Liu, Freeman Zhong:
Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced Traffics. ISCAS 2007: 2132-2135 - [c1]Yikui Dong, Steve Howard, Freeman Zhong, Scott Lowrie, Ken Paradis, Jan Kolnik, Jeff Burleson:
AC-coupling strategy for high-speed transceivers of 10Gbps and beyond. VLSI-SoC 2007: 84-87 - 2005
- [j1]Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Catherine Chow, Ratnakar Dadi, Chintan Desai, Leo Fang, David Hsu, Pankaj Joshi, Hiroshi Kimura, Cathy Ye Liu, Tzu-Wang Pan, Ryan Park, Cindy You, Yi Zeng, Eric Zhang, Freeman Zhong:
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization. IEEE J. Solid State Circuits 40(9): 1957-1967 (2005)
Coauthor Index
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