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ORCIDHyo-Gyuem Rhew
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2020 – today
- 2026
[j6]Hyo Gyuem Rhew, Heein Yoon, Chia-Hsiang Yang, Utsav Banerjee, Xueqing Li:
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 61(1): 4-7 (2026)- 2025
- [j5]Chang Liu
, Burak Catli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Xiaochen Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao:
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm. IEEE Solid State Circuits Lett. 8: 281-284 (2025) - [c12]Chang Liu, Burak Çatli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Alex Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao:
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm. CICC 2025: 1-3 - [c11]Bohdan Karpinskyy, Yong Ki Lee, Sumin Noh, Yunhyeok Choi, Jieun Park, Jisu Kang, Taewook Park, Eunhye Oh, Gapkyung Kim, Sungha Lee, Hyunwoo Ko, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin:
An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies. ISSCC 2025: 1-3 - 2024
- [j4]Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo Gyuem Rhew, Jongshin Shin:
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. IEEE J. Solid State Circuits 59(1): 231-242 (2024) - [c10]Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeom-Je Bae, Youngseob Suh, Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin:
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. ISSCC 2024: 250-252 - [c9]Jieun Park, Yong Ki Lee, Bohdan Karpinskyy, Yunhyeok Choi, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin:
16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm. ISSCC 2024: 310-312 - [c8]Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao:
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. ISSCC 2024: 338-340 - 2023
- [j3]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - [c7]Kihwan Seong, Donguk Park, Gyeom-Je Bae, Hyunwoo Lee, Youngseob Suh, Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin:
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. ISSCC 2023: 114-115 - [c6]Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin:
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. ISSCC 2023: 406-407 - 2022
- [c5]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c4]Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169
2010 – 2019
- 2016
- [c3]Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao:
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS. ISSCC 2016: 58-59 - 2014
- [j2]Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. IEEE J. Solid State Circuits 49(10): 2213-2227 (2014) - 2012
- [c2]Hyo Gyuem Rhew, Michael P. Flynn, JunYoung Park:
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. ESSCIRC 2012: 233-236 - [c1]Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. VLSIC 2012: 70-71 - 2010
- [j1]Jongwoo Lee, Hyo-Gyuem Rhew, Daryl R. Kipke, Michael P. Flynn:
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. IEEE J. Solid State Circuits 45(9): 1935-1945 (2010)
Coauthor Index
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