Microprocessor Test/Validation

• 
  Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina: At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. 3-8
• 
  Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. 9-14
• 
  Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng: On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. 15-22

Low Power BIST and Scan

• 
  Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Low Power/Energy BIST Scheme for Datapaths. 23-28
• 
  Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Low Power BIST via Non-Linear Hybrid Cellular Automata. 29-34
• 
  Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba: Static Compaction Techniques to Control Scan Vector Power Dissipation. 35-42

Technology Trends and Their Impact on Test

• 
  R. Dean Adams, Phil Shephard III: Silicon-on-Insulator Technology Impacts on SRAM Testing. 43-48
• 
  Byungwoo Choi, D. M. H. Walker: Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. 49-54
• 
  Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal: Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. 55-66

Scan Related Approaches

• 
  Frank P. Higgins, Rajagopalan Srinivasan: BSM2: Next Generation Boundary-Scan Master. 67-72
• 
  Abhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. 73-78
• 
  Jayabrata Ghosh-Dastidar, Nur A. Touba: A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. 79-88

Defect Driven Techniques

• 
  Hugo Cheung, Sandeep K. Gupta: A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. 89-96
• 
  Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee: Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. 97-104
• 
  Chul Young Lee, D. M. H. Walker: PROBE: A PPSFP Simulator for Resistive Bridging Faults. 105-112

System-on-chip Test Techniques

• 
  Anshuman Chandra, Krishnendu Chakrabarty: Test Data Compression for System-on-a-Chip Using Golomb Codes. 113-120
• 
  A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su: Test and Debug of Networking SoCs: A Case Study. 121-126
• 
  Krishnendu Chakrabarty: Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. 127-136

Analog Test Techniques

• 
  Ramakrishna Voorakaranam, Abhijit Chatterjee: Test Generation for Accurate Prediction of Analog Specifications. 137-142
• 
  Jeongjin Roh, Jacob A. Abraham: A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. 143-148
• 
  Sule Ozev, Alex Orailoglu: Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. 149-156

BIST: Arithmetic, Memories and ILAs

• 
  Vivek Chickermane, Scott Richter, Carl Barnhart: Integrating Logic BIST in VLSI Designs with Embedded Memories. 157-164
• 
  Albrecht P. Stroele: Synthesis for Arithmetic Built-In Self-Tes. 165-170
• 
  Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu: General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. 171-178

Embedded Tutorial

• 
  M. S. Huetmaker: RF/Analog Test of Circuits and Systems. 179-182

Temperature and Process Drift Issues

• 
  Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu: Cold Delay Defect Screening. 183-188
• 
  Josep Altet, Antonio Rubio, E. Schaub, Stefan Dilhaire, Wilfrid Claeys: Thermal Testing: Fault Location Strategies. 189-194
• 
  Amy Germida, James F. Plusquellic: Detection of CMOS Defects under Variable Processing Conditions. 195-204

Test Compaction and Design Validation

• 
  Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. 205-212
• 
  Markus Seuring, Krishnendu Chakrabarty: Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions. 213-220
• 
  Hussain Al-Asaad, John P. Hayes: ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. 221-230

Analog BIST

• 
  Seongwon Kim, Mani Soma, Dilip Risbud: An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. 231-236
• 
  Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng: Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. 237-246
• 
  Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand: Hardware Resource Minimization for Histogram-Based ADC BIST. 247-254

Functional Test and Verification Issues

• 
  Li Chen, Sujit Dey: DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. 255-262
• 
  Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. 263-270
• 
  Katarzyna Radecka, Zeljko Zilic: Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. 271-280

Memory Test

• 
  A. J. van de Goor, Zaid Al-Ars: Functional Memory Faults: A Formal Notation and a Taxonomy. 281-290
• 
  Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu: Simulation-Based Test Algorithm Generation for Random Access Memories. 291-296
• 
  Jun Zhao, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi: Detection of Inter-Port Faults in Multi-Port Static RAMs. 297-304

Open Defect Detection, Diagnosis and Analog BIS

• 
  Víctor H. Champac, Antonio Zenteno: Detectability Conditions for Interconnection Open Defect. 305-312
• 
  Srikanth Venkataraman, Scott Brady Drummonds: A Technique for Logic Fault Diagnosis of Interconnect Open Defects. 313-318
• 
  José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski: Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. 319-324

Open Projector

• 
  T. W. Williams, Stephen K. Sunter: How Should Fault Coverage Be Defined? 325-328

Panel

• 
  Bapiraju Vinnakota, André Ivanov: Biomedical ICs: What is Different about Testing those ICs? 329-332

Delay Test, Diagnosis and BIST

• 
  Manish Sharma, Janak H. Patel: Bounding Circuit Delay by Testing a Very Small Subset of Paths. 333-342
• 
  Ramesh C. Tekumalla: On Test Set Generation for Efficient Path Delay Fault Diagnosis. 343-348
• 
  Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev: A Low-Speed BIST Framework for High-Performance Circuit Testing. 349-358

BIST Issues

• 
  Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault: Hidden Markov and Independence Models with Patterns for Sequential BIST. 359-368
• 
  Ilker Hamzaoglu, Janak H. Patel: Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. 369-376
• 
  Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. 377-388

STIL Extension, Jitter, and Crosstalk

• 
  Peter Wohl, Nathan Biggs: P1450.1: STIL for the Simulation Environmen. 389-394
• 
  Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi: Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. 395-402
• 
  Chauchin Su, Yue-Tsang Chen: Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. 403-410

High Level ATPG and Test Scheduling

• 
  Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero: High-Level Observability for Effective High-Level ATPG. 411-416
• 
  Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. 417-422
• 
  Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi: Testability Alternatives Exploration through Functional Testing. 423-430

IDDQ Test

• 
  Claude Thibeault: Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. 431-438
• 
  Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce: Delta Iddq for Testing Reliability. 439-443
• 
  Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana: Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs. 444-452

On-line Testing and Fault Tolerance

• 
  Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Fault Escapes in Duplex Systems. 453-458
• 
  Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu: Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. 459-464
• 
  Subhasish Mitra, Edward J. McCluskey: Word Voter: A New Voter Design for Triple Modular Redundant Systems. 465-470

Panels

• 
  Fidel Muradali, André Ivanov: Do I Need this Tool for My Chips to Work? 471-472
• 
  Melvin A. Breuer: High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. 473-474

last updated on Sat May 25 05:42:58 2013 by the dblp team
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