47. DAC 2010:
Anaheim,
CA,
USA
Sachin S. Sapatnekar (Ed.):
Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010.
ACM 2010, ISBN 978-1-4503-0002-5 
Panel
Special session:
Post-silicon validation or avoiding the $50 million paperweight
Speed up your model! RTL,
data-flow,
or SystemC
Embedded software timing matters!
Thermal tracking,
monitoring and characterization
Advanced clock design and flip-chip layout
- Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis:
Non-uniform clock mesh optimization with linear programming buffer insertion.
74-79
- Xin-Wei Shih, Yao-Wen Chang:
Fast timing-model independent buffered clock-tree synthesis.
80-85
- Ying-Yu Chen, Chen Dong, Deming Chen:
Clock tree synthesis under aggressive buffer insertion.
86-89
- Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng:
Global routing and track assignment for flip-chip designs.
90-93
Panel
Special session:
Virtualization in the embedded systems:
where do we go?
Memory and multiprocessor design space exploration
- Giovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano:
A correlation-based design space exploration methodology for multi-processor systems-on-chip.
120-125
- Jishen Zhao, Xiangyu Dong, Yuan Xie:
Cost-aware three-dimensional (3D) many-core multiprocessor design.
126-131
- Chenjie Yu, Peter Petrov:
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.
132-137
- Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun:
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
138-143
Interconnect networks:
present and future
- Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel Loh, Alok N. Choudhary:
Quantifying and coping with parametric variations in 3D-stacked microarchitectures.
144-149
- Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li:
Cost-driven 3D integration with interconnect layers.
150-155
- Xiang Zhang, Ahmed Louri:
A multilayer nanophotonic interconnection network for on-chip many-core communications.
156-161
- Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni:
Virtual channels vs. multiple physical networks: a comparative analysis.
162-165
- Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol:
An efficient dynamically reconfigurable on-chip network architecture.
166-169
Core techniques in formal verification
New frontiers in routing
Panel
Special session:
Joint DAC/IWBDA special session engineering biology:
fundamentals and applications
Reliability and integrity of circuits and systems
Embedded hardware for security,
data type refinement,
and arbitration
- Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system.
240-243
- Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner:
Theoretical analysis of gate level information flow tracking.
244-247
- David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor:
Exploiting finite precision information to guide data-flow mapping.
248-253
- Adam B. Kinsman, Nicola Nicolici:
Robust design methods for hardware accelerators for iterative algorithms in scientific computing.
254-257
- Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang:
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.
258-261
Statistical techniques for silicon-to-model correlation
Placement:
from traditional techniques to novel circuit styles
Panel
Special session:
A decade of NOC research - where do we stand?
Exploiting concurrency for system-level performance
Data Access Times Define Performance!
- Guangdeng Liao, Heeyeol Yu, Laxmi N. Bhuyan:
A new IP lookup cache for high performance IP routers.
338-343
- Yun Liang, Tulika Mitra:
Instruction cache locking using temporal reuse profile.
344-349
- Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He, Meikang Qiu, Edwin Hsing-Mean Sha:
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.
350-355
- Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
356-361
Tools for effective post-silicon validation and test
- Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski:
Fully X-tolerant, very high scan compression.
362-367
- Sung-Boem Park, Anne Bracy, Hong Wang, Subhasish Mitra:
BLoG: post-silicon bug localization in processors using bug localization graphs.
368-373
- Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir:
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.
374-379
- Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin:
Efficient fault simulation on many-core processors.
380-385
Shapes and statistics:
manufacturability and yield
Panel
Special session:
The analog model crisis - how can we solve it?
Application-driven network-on-chip design
- Colin J. Ihrig, Rami G. Melhem, Alex K. Jones:
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors.
431-436
- Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam:
Trace-driven optimization of networks-on-chip configurations.
437-442
- Jason Cong, Chunyue Liu, Glenn Reinman:
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.
443-448
- Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng:
NTPT: on the end-to-end traffic prediction in the on-chip networks.
449-452
- Wooyoung Jang, David Z. Pan:
Application-aware NoC design for efficient SDRAM access.
453-456
Exploiting FPGA-specific features for robustness and efficiency
- Kaveh Elizeh, Nicola Nicolici:
Embedded memory binding in FPGAs.
457-462
- Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors.
463-468
- Manu Jose, Yu Hu, Rupak Majumdar, Lei He:
Rewiring for robustness.
469-474
Leakage estimation and optimization
Logic synthesis is alive and kicking
Panel
Special session:
Design closure for reliability
Energy-efficient embedded hardware design and management
- Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal:
Xetal-Pro: an ultra-low energy and high throughput SIMD processor.
543-548
- Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor:
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
549-554
- Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
555-560
Parallel and efficient techniques in circuit simulation
- Xiaoji Ye, Peng Li:
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation.
561-566
- Yong Zhang, Peng Li, Garng M. Huang:
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis.
567-572
- Xuexin Liu, Hao Yu, Sheldon X.-D. Tan:
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.
573-578
Thermal management and optimization
Catch of the day in benchmarking and optimal synthesis
- Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma:
Eyecharts: constructive benchmarking of gate sizing heuristics.
597-602
- Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists.
603-608
- Mustafa Altun, Marc D. Riedel:
Lattice-based computation of Boolean functions.
609-612
- Jason Thong, Nicola Nicolici:
A novel optimal single constant multiplication algorithm.
613-616
Panel
Special session:
WACI:
wild and crazy ideas
- Chen-Ling Chou, Anca M. Miron, Radu Marculescu:
Find your flow: increasing flow experience by designing "human" embedded systems.
619-620
- Andrew DeOrio, Valeria Bertacco:
Electronic design automation for social networks.
621-622
- Azalia Mirhoseini, Yousra Alkabani, Farinaz Koushanfar:
Real time emulations: foundation and applications.
623-624
- Cristinel Ababei:
Network on chip design and optimization using specialized influence models.
625-626
- Dean Truong, Bevan M. Baas:
Circuit modeling for practical many-core architecture design exploration.
627-628
- Farinaz Koushanfar:
Hierarchical hybrid power supply networks.
629-630
- Shinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong:
Detachable nano-carbon chip with ultra low power.
631-632
- Miodrag Potkonjak:
Synthesis of trustable ICs using untrusted CAD tools.
633-634
Algorithms and architectures for emerging technologies
- Yang Zhao, Krishnendu Chakrabarty:
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips.
635-640
- Cliff Chiung-Yu Lin, Yao-Wen Chang:
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips.
641-646
- Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the number of lines in reversible circuits.
647-652
- Oleg Golubitsky, Sean M. Falconer, Dmitri Maslov:
Synthesis of the optimal 4-bit reversible circuits.
653-656
- Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu:
Crosstalk noise and bit error rate analysis for optical network-on-chip.
657-660
Simulation and modeling techniques for devices and interconnect
- Zhuo Feng, Zhiyu Zeng:
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis.
661-666
- Tarek A. El-Moselhy, Luca Daniel:
Stochastic dominant singular vectors method for variation-aware extraction.
667-672
- Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David Blaauw:
Closed-form modeling of layout-dependent mechanical stress.
673-678
- Sanda Lefteriu, Jan Mohring:
Generating parametric models from tabulated data.
679-682
- Yuanzhe Wang, Chi-Un Lei, Grantham K. H. Pang, Ngai Wong:
MFTI: matrix-format tangential interpolation for modeling multi-port systems.
683-686
Design of ultra low-power systems
Variation-aware methods for SRAMs and clocks
- Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark:
In-situ characterization and extraction of SRAM variability.
711-716
- Paul Zuber, Petr Dobrovolný, Miguel Miranda:
A holistic approach for statistical SRAM analysis.
717-722
- Tak-Yung Kim, Taewhan Kim:
Clock tree synthesis with pre-bond testability for 3D stacked IC designs.
723-728
- Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
An efficient phase detector connection structure for the skew synchronization system.
729-734
Joint user track panel:
What will make your next design experience a much better one?
Special session:
Cyber-physical systems demystified
Application and improvement of dynamic verification
- Wenchao Li, Alessandro Forin, Sanjit A. Seshia:
Scalable specification mining for verification and diagnosis.
755-760
- Bo D. Wang, Yuhao Zhu, Yangdong Deng:
Distributed time, conservative parallel logic simulation on GPUs.
761-766
- ByongChan Lim, Jaeha Kim, Mark A. Horowitz:
An efficient test vector generation for checking analog/mixed-signal functional models.
767-772
- Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha:
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
773-776
- Morteza Fayyazi, Laurent Kirsch:
Efficient simulation of oscillatory combinational loops.
777-780
Timing analysis and circuit optimization for novel technologies and DFM
- Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu:
Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
781-786
- Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
RDE-based transistor-level gate simulation for statistical static timing analysis.
787-792
- Vineeth Veetil, Yung-Hsu Chang, Dennis Sylvester, David Blaauw:
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization.
793-798
- Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li:
Static timing analysis for flexible TFT circuits.
799-802
- Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan:
TSV stress aware timing analysis with applications to 3D-IC layout optimization.
803-806
System power modeling and management
Management of power integrity and circuit reliability
- Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li:
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.
831-836
- Xuanxing Xiong, Jia Wang:
An efficient dual algorithm for vectorless power grid verification under linear current constraints.
837-842
- Xueqian Zhao, Yonghe Guo, Zhuo Feng, Shiyan Hu:
Parallel hierarchical cross entropy optimization for on-chip decap budgeting.
843-848
- Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan:
SRAM-based NBTI/PBTI sensor system design.
849-852
- Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells.
853-856
Panel
Special session:
Computing without guarantees
Design and modeling of technologies beyond CMOS
- Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie:
Impact of process variations on emerging memristor.
877-882
- Sansiri Tanachutiwat, Ji Ung Lee, Wei Wang, Chun Yung Sung:
Reconfigurable multi-function logic based on graphene P-N junctions.
883-888
- Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra:
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
889-892
- Hamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee:
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.
893-896
Yield-aware optimization and modeling for analog circuits
- Wangyang Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li:
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression.
897-902
- Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits.
903-908
- Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa:
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.
909-912
- Amith Singhee, Pamela Castalino:
Pareto sampling: choosing the right weights by derivative pursuit.
913-916
Reducing the cost of test
Special session:
Smart power:
from your cell phone to your home
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