46. DAC 2009: San Francisco, CA, USA


Mechanisms for surviving uncertainty: opportunities and prospects

Combating non-idealities in static timing analysis

High-performance platforms: advances in system-level exploration and optimization

Novel design and verification methodologies

Design and optimization of nanocircuits


Dawn of the 22nm design era - yes we can!

Statistical methods in static timing analysis

Profiling, test and debug of embedded systems

Low-power design and analysis techniques

Design integrity challenges


Verifying an SOC monster: whose job is it anyway?

Timing simulation: optimized embedded software and MPSOCs

Advances in embedded system modeling and optimization

Interconnect optimization for emerging technologies

Design flexibility: bend it, shape it, anyway you want it!


Emerging technologies: blue-sky research or CMOS replacement?

Routing: from chip to package

Speed path identification and silicon debug

Analog/RF simulation and statistical modeling

Recent advances in timing, ECO and logic optimization


Computation in the post-Turing era

Advances in physical synthesis

Jumping the high-level verification hurdle

Thermal optimization

Novel techniques to minimize circuit failure


Multicore computing and EDA

Layout-based variability modeling and optimization

Advances in core verification techniques

Future interconnect technologies: how do on-chip networks evolve?

Robust analog system design

WACI: wild and crazy ideas

The tool shows that my design is wrong, but where is the bug?