ICCAD 1992:
Santa Clara, California, USADFT to Reduce Test Application Time
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Y. H. Choi ,
T. Jung :
Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices.
13-16
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Technology Driven Layout
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Lookup Table Based FPGA Synthesis Techniques
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Jason Cong ,
Yuzheng Ding :
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
48-53
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Advances in Asymptotic Waveform Evaluation
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Topics in Simulation
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Daniel Brand :
Exhaustive simulation need not require an exponential number of tests.
98-101
Asynchronous Circuit Synthesis Using STG's
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conf/iccad/VanbekbergenLGM92 export record as
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Clocking of Circuits with Level Sensitive Latches
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High Density Module Assembly
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conf/iccad/VaradarajanB92 export record as
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Formal Hardware Verification
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Techniques for Power and Timing Estimation in CMOS Circuits
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conf/iccad/Nabavi-LishiR92 export record as
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Sequential ATPG
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High-Level Design
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Classical Simulation
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Testing and Diagnosis Methods
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DSP Applications in High-Level Synthesis
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conf/iccad/VerhaeghLAKWM92 export record as
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conf/iccad/ChandrakasanPRB92 export record as
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Analog CAD
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conf/iccad/FernandezRMH92 export record as
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Multi-View Design Representations for Interactive Synthesis
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Timing in High Level Synthesis
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Leon Stok :
False loops through resource sharing.
345-348
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conf/iccad/RamachandranKGWC92
Techniques for High Performance Simulation
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conf/iccad/SuganumaMNNTH92 export record as
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Detailed Routing
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Topics in Logic Synthesis
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Seh-Woong Jeong ,
Fabio Somenzi :
A new algorithm for the binate covering problem and its application to the minimization of Boolean relations.
417-420
Partitioning and Clustering
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Interconnect Analysis
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Ali El-Zein ,
Salim Chowdhury :
An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines.
443-448
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Panel
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High-Performance Routing
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Hardware/Software Co-Design and System Design
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H. Krämer ,
J. Müller :
Assignment of global memory elements for multi-process VHDL specifications.
496-501
Retiming and Sensitization Conditions
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Design Management Styles
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Delay Testing
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Kwang-Ting Cheng :
Test generation for delay faults in non-scan and partial scan sequential circuits.
554-559
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Asynchronous Synthesis
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Placement and Floorplan Design
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High-Level View of Testing
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conf/iccad/ChickermaneLP92
Hazards in Combinatorial Synthesis
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David S. Kung :
Hazard-non-increasing gate-level optimization algorithms.
631-634
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