Daniel G. Schweikert (Ed.):
Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992.
IEEE Computer Society Press 1992, ISBN 0-8186-2822-7
29. DAC 1992:
Anaheim, California, USA
Two Level Logic Synthesis
Partitioning and Floorplanning
Scheduling and Allocation
: Is Technology-Independent Design Really Practical? (Panel Abstract).
New Approaches to Placement
Synthesis Systems and Representations
: Which ASIC Technology Will Dominate the 1990's (Panel Abstract).
Asymptotic Waveform Evaluation
Performance Issues in Logic Synthesis
: Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract).
High-Level Test Generation
Allocation and Binding
: Why it doesn't work for CAD (Panel Abstract).
: Directions to Watch in Design Technology (Tutorial Abstract).
Design Verification and Compaction
: An Interpreter for General Netlist Design Rule Checking.
David G. Boyer
: Process Independent Constraint Graph Compaction.
Fault Simulation and Fault Diagnosis
Hyung Ki Lee
, Dong Sam Ha
: HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits.
Timing Optimization and Verification
Larry G. Jones
: Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator.
: Performance Evaluation of an Event-Driven Logic Simulation Machine.
Multi-Level Logic Synthesis
Abdul A. Malik
: Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization.
: Design and Integration Services (Panel Abstract).
DA for High-Speed Packaging
Technology Mapping in Logic Synthesis
: Why is Today's CAD Inadequate for Designing Tomorrow's Computers (Panel Abstract).
, Ching-Long Su
, Ing-Jer Huang
, Kuo-Rueih Pan
, Yong-Seon Koh
, Chi-Ying Tsui
, Hsu-Tsun Chen
, Gino Cheng
, Shihming Liu
, Shiqun Wu
, Alvin M. Despain
: Application-Driven Design Automation for Microprocessor Design.
Global Issues in Routing
Path Delay Analysis
Sequential Logic Synthesis
: Frameworks - User's Perspective (Panel Abstract).
Multi-Layer Channel and Over-the-Cell Routing
: New Models for Four- and Five-Layer Channel Routing.
Automated Approaches to Formal Verification of Hardware
Advances in High-Level Synthesis
Tutorial - EDIF/CFI - A User's Perspective
Routing for Special Applications
, Sumio Oguri
: An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style.
: Plane Parallel a Maze Router and Its Application to FPGAs.
Issues in Analog CAD
, Jacob White
: Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics.