29. DAC 1992:
Anaheim, California, USA Daniel G. Schweikert (Ed.):
Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992.
IEEE Computer Society Press 1992, ISBN 0-8186-2822-7 Electrical Analysis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Test Generation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Two Level Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Tutorial
export record as
dblp key:
Partitioning and Floorplanning
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Interconnect Simulation
export record as
dblp key:
conf/dac/RoychowdhuryNP92 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
David D. Ling ,
S. Kim ,
J. White :
A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect.
93-98
Scheduling and Allocation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel
export record as
dblp key:
Peter Hillen :
Is Technology-Independent Design Really Practical? (Panel Abstract).
128
Concurrent Engineering
export record as
dblp key:
export record as
dblp key:
New Approaches to Placement
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Deley-Fault Testing
export record as
dblp key:
conf/dac/BhattacharyaAA92 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Synthesis Systems and Representations
export record as
dblp key:
export record as
dblp key:
A. Stoll ,
Peter Duzy :
High-Level Synthesis from VHDL with Exact Timing Constraints.
188-193
export record as
dblp key:
Panel
export record as
dblp key:
Ronald Collet :
Which ASIC Technology Will Dominate the 1990's (Panel Abstract).
200
Asymptotic Waveform Evaluation
export record as
dblp key:
export record as
dblp key:
conf/dac/AnastasakisGKP92 export record as
dblp key:
System-Level Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Performance Issues in Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel
export record as
dblp key:
William Lattin :
Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract).
260
High-Level Test Generation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/dac/VishakantaiahAA92
Allocation and Binding
export record as
dblp key:
conf/dac/KrishnamoorthyN92 export record as
dblp key:
export record as
dblp key:
conf/dac/RundensteinerG92
Panel
export record as
dblp key:
Rick Potter :
Why it doesn't work for CAD (Panel Abstract).
297
Tutorial
export record as
dblp key:
Gerry Langeler :
Directions to Watch in Design Technology (Tutorial Abstract).
298
Design Verification and Compaction
export record as
dblp key:
export record as
dblp key:
Georg Peltz :
An Interpreter for General Netlist Design Rule Checking.
305-310
export record as
dblp key:
export record as
dblp key:
David G. Boyer :
Process Independent Constraint Graph Compaction.
318-322
export record as
dblp key:
Fault Simulation and Fault Diagnosis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Hyung Ki Lee ,
Dong Sam Ha :
HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits.
336-340
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
FPGA Synthesis
export record as
dblp key:
Kevin Chung ,
Jonathan Rose :
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections.
361-367
export record as
dblp key:
export record as
dblp key:
conf/dac/SchlichtmannBH92 export record as
dblp key:
Tutorial
export record as
dblp key:
Timing Optimization and Verification
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Discrete Simulation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Larry G. Jones :
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator.
424-427
export record as
dblp key:
Fumiyasu Hirose :
Performance Evaluation of an Event-Driven Logic Simulation Machine.
428-431
export record as
dblp key:
Multi-Level Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Abdul A. Malik :
Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization.
449-453
export record as
dblp key:
Panel
export record as
dblp key:
Ronald Collet :
Design and Integration Services (Panel Abstract).
459
DA for High-Speed Packaging
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Technology Mapping in Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
John P. Fishburn :
LATTIS: An Iterative Speedup Heuristic for Mapped Logic.
488-491
export record as
dblp key:
Panel
export record as
dblp key:
Arny Goldfein :
Why is Today's CAD Inadequate for Designing Tomorrow's Computers (Panel Abstract).
499
Frameworks
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Iksoo Pyo ,
Ching-Long Su ,
Ing-Jer Huang ,
Kuo-Rueih Pan ,
Yong-Seon Koh ,
Chi-Ying Tsui ,
Hsu-Tsun Chen ,
Gino Cheng ,
Shihming Liu ,
Shiqun Wu ,
Alvin M. Despain :
Application-Driven Design Automation for Microprocessor Design.
512-517
Global Issues in Routing
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Path Delay Analysis
export record as
dblp key:
Jon Frankle :
Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing.
536-542
export record as
dblp key:
export record as
dblp key:
Sequential Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel
export record as
dblp key:
L. Lanzo :
Frameworks - User's Perspective (Panel Abstract).
578
Multi-Layer Channel and Over-the-Cell Routing
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Tai-Tsung Ho :
New Models for Four- and Five-Layer Channel Routing.
589-593
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Automated Approaches to Formal Verification of Hardware
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Advances in High-Level Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Ruchir Puri ,
Jun Gu :
An Efficient algorithm for Microword Length Minimization.
651-656
export record as
dblp key:
export record as
dblp key:
Tutorial - EDIF/CFI - A User's Perspective
export record as
dblp key:
export record as
dblp key:
Routing for Special Applications
export record as
dblp key:
Ryosuke Okuda ,
Sumio Oguri :
An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style.
676-681
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Mikael Palczewski :
Plane Parallel a Maze Router and Its Application to FPGAs.
691-697
Issues in Analog CAD
export record as
dblp key:
export record as
dblp key:
conf/dac/DharchoudhuryK92 export record as
dblp key:
Keith Nabors ,
Jacob White :
Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics.
710-715
Panels
export record as
dblp key:
export record as
dblp key:
data released under the ODC-BY 1.0 license
