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ORCID18th Asian Test Symposium 2009: Taichung, Taiwan
- Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan. IEEE Computer Society 2009, ISBN 978-0-7695-3864-8
Built-In Self-Test
- Sukanta Das, Biplab K. Sikdar
:
CA Based Built-In Self-Test Structure for SoC. 3-8 - Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
A Random Jitter RMS Estimation Technique for BIST Applications. 9-14 - Rupsa Chakraborty, Dipanwita Roy Chowdhury:
A Novel Seed Selection Algorithm for Test Time Reduction in BIST. 15-20 - Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang:
Logic BIST Architecture for System-Level Test and Diagnosis. 21-26
Fault Diagnosis
- Irith Pomeranz, Sudhakar M. Reddy:
Fault Diagnosis under Transparent-Scan. 29-34 - Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen:
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. 35-40 - Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang:
On Improving Diagnostic Test Generation for Scan Chain Failures. 41-46 - Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson:
On Scan Chain Diagnosis for Intermittent Faults. 47-54
Analog and Mixed-Signal Testing I
- Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang:
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. 57-62 - Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. 63-68 - Sehun Kook, Hyun Woo Choi, Vishwanath Natarajan, Abhijit Chatterjee, Alfred V. Gomes, Shalabh Goyal, Le Jin:
Low Cost Dynamic Test Methodology for High Precision ΣD ADCs. 69-74 - Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng:
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. 75-80
Industrial Session
- Dragon Hsu, Ron Press:
Scan Compression Implementation in Industrial Design - Case Study. 83-84 - Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng:
Calibration as a Functional Test: An ADC Case Study. 85-86 - Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu:
Customized Algorithms for High Performance Memory Test in Advanced Technology Node. 87-89 - Augusli Kifli, Y. W. Chen, Yu-Wen Tsai, Kun-Cheng Wu:
A Practical DFT Approach for Complex Low Power Designs. 90-91 - Mukund Mittal, Subrangshu Das, S. Vishwanath:
DFT Challenges in Next Generation Multi-media IP. 92-93 - Feng-Ming Kuo, Yuan-Shih Chen:
Yield Ramp up by Scan Chain Diagnosis. 94-95
Low-Power Testing
- Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa:
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. 99-104 - Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau:
New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology. 105-110 - Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu:
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. 111-116
On-Line Testing and Silicon Debug
- Ming Gao, Kwang-Ting Cheng:
Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder. 119-124 - Stefano Di Carlo, Paolo Prinetto, Alberto Scionti:
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems. 125-130 - Sandesh Prabhakar, Michael S. Hsiao:
Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug. 131-136 - Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
A Post-Silicon Debug Support Using High-Level Design Description. 137-142
Delay Testing
- Songwei Pei, Huawei Li, Xiaowei Li:
A Low Overhead On-Chip Path Delay Measurement Circuit. 145-150 - Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu:
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. 151-156 - Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito:
A Delay Measurement Technique Using Signature Registers. 157-162 - Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li:
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. 163-168
Test Generation I
- Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue:
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. 171-176 - Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. 177-182 - Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
N-distinguishing Tests for Enhanced Defect Diagnosis. 183-186 - Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
Dynamic Compaction in SAT-Based ATPG. 187-190
System Test
- Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. 193-199 - Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su:
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. 200-205 - Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh:
Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors. 206-211
Panel Session I
- Anis Uzzaman:
Is Low Power Testing Necessary? What does the Test Industry Truly Need?. 215-216
DFT
- Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu:
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. 219-224 - Michael S. Hsiao, Mainak Banga:
Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time. 225-230 - Katherine Shu-Min Li, Yu-Chen Hung, Jr-Yang Huang:
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint. 231-236 - K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh:
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. 237-240
RF and Analog Testing
- Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee:
BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search. 243-248 - Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee:
Self-Calibrating Embedded RF Down-Conversion Mixers. 249-254 - Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. 255-260 - Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir:
Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE. 261-266
SoC Test
- Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang:
IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. 269-274 - Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, Jing-Jia Liou:
Multiple-Core under Test Architecture for HOY Wireless Testing Platform. 275-280 - Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. 281-286 - Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu:
Test Integration for SOC Supporting Very Low-Cost Testers. 287-292
Test Generation II
- Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman:
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. 295-300 - Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
New Class of Tests for Open Faults with Considering Adjacent Lines. 301-306 - Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay:
Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. 307-312 - Görschwin Fey:
Deterministic Algorithms for ATPG under Leakage Constraints. 313-316
Test Data Compression
- Jun Liu, Yinhe Han, Xiaowei Li:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. 319-324 - Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee:
A Multi-dimensional Pattern Run-Length Method for Test Data Compression. 325-330 - Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji:
Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. 331-336
Panel Session II
- Said Hamdioui:
Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?. 339
Fault Modeling & Diagnosis
- Ying-Yen Chen, Jing-Jia Liou:
A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. 343-348 - Po-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao:
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. 349-354 - Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. 355-360 - Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings:
A Partially-Exhaustive Gate Transition Fault Model. 361-364
Analog and Mixed-Signal Testing II
- Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang:
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. 367-372 - Joonsung Park, Jaeyong Chung, Jacob A. Abraham:
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. 373-378 - An-Sheng Chao, Soon-Jyh Chang:
A Jitter Characterizing BIST with Pulse-Amplifying Technique. 379-384 - Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang:
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method. 385-388
Memory Test
- Ad J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars:
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. 391-396 - Yu-Jen Huang, Jin-Fu Li:
Testability Exploration of 3-D RAMs and CAMs. 397-402 - Zaid Al-Ars, Said Hamdioui:
Fault Diagnosis Using Test Primitives in Random Access Memories. 403-408
Test Generation III
- Xijiang Lin, Mark Kassab:
Test Generation for Designs with On-Chip Clock Generators. 411-417 - Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda:
On the Generation of Functional Test Programs for the Cache Replacement Logic. 418-423 - Dong Xiang, Boxue Yin, Krishnendu Chakrabarty:
Compact Test Generation for Small-Delay Defects Using Testable-Path Information. 424-429 - Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng:
At-Speed Scan Test Method for the Timing Optimization and Calibration. 430-433
Defect-Based Testing
- Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan:
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. 437-442 - Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu:
Analysis of Resistive Bridging Defects in a Synchronizer. 443-449 - Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. 450-455 - Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu:
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks. 456-461
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