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ORCIDIntegration, Volume 62
Volume 62, June 2018
- Pooran Singh
, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. 1-13 - Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. 14-23 - Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee:
Contention free delayed keeper for high density large signal sensing memory compiler. 24-33 - Mohammad Danaie, Esmaeel Ranjbar, Mojtaba Ahmadieh Khanesar:
MOSCAP compensation of three-stage operational amplifiers: Sensitivity and robustness, modeling and analysis. 34-49 - Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar:
Offline Testing of Reversible Logic Circuits: An Analysis. 50-67 - Mohammad Sadeghi, Hooman Nikmehr:
Aging mitigation of L1 cache by exchanging instruction and data caches. 68-75 - Tze Sin Tan, Bakhtiar Affendi Rosdi:
Hardware-assisted Verilog simulation system using an application specific microprocessor. 76-91 - Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay:
Reliability-aware application mapping onto mesh based Network-on-Chip. 92-113 - Ismail Bayram, Yiran Chen:
NV-TCAM: Alternative designs with NVM devices. 114-122 - Mohamed Khairy Bahry, Mohamed El-Nozahi, Emad Hegazi:
An all-digital low ripples capacitive DC-DC converter with load tracking controller. 123-131 - Paria Jamshidi, Mohammad Maymandi-Nejad:
Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators. 132-141 - Adam Opara, Marcin Kubica, Dariusz Kania:
Strategy of logic synthesis using MTBDD dedicated to FPGA. 142-158 - Safa Berrima, Yves Blaquière, Yvon Savaria:
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. 159-169 - M. Mohamed Asan Basiri, Sandeep K. Shukla:
Low power hardware implementations for network packet processing elements. 170-181 - Chang Liu, Xu He, Bin Liang, Yang Guo:
Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. 182-189 - Stefan Kristofík, Peter Malík:
Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults. 190-204 - Nadia Nedjah, Heloisa Dina Bezerra, Luiza de Macedo Mourelle:
Automatic generation of harmonious music using cellular automata based hardware design. 205-223 - Etienne Lepercq, Yves Blaquière, Yvon Savaria:
A pattern-based routing algorithm for a novel electronic system prototyping platform. 224-237 - J. Ahmadi-Farsani, Hamed Sadjedi, M. B. Ghaznavi-Ghoushchi:
An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm. 238-245 - Aili Wang, Chuanjin Richard Shi:
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. 246-257 - Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari:
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology. 258-269 - Dimitrios Balobas, Nikos Konofaos:
High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS. 270-281 - Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer:
Accelerating cycle-accurate system-level simulations through behavioral templates. 282-291 - Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou:
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. 292-300 - Tuotian Liao, Lihong Zhang:
Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits. 301-313 - Murat Pak, Francisco V. Fernández, Günhan Dündar:
A novel design methodology for the mixed-domain optimization of a MEMS accelerometer. 314-321 - Xiao Zhao, Yongqing Wang, Liyuan Dong:
Super current recycling folded cascode amplifier with ultra-high current efficiency. 322-328 - Ioannis A. Papistas, Vasilis F. Pavlidis:
Contactless Heterogeneous 3-D ICs for Smart Sensing Systems. 329-340 - Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. 341-352 - Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi:
A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates. 353-361 - Mohammad Abdel-Majeed, Waleed Dweik:
Low overhead online periodic testing for GPGPUs. 362-370 - Amir Ardakani, Shahriar B. Shokouhi, Arash Reyhani-Masoleh:
Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines. 371-381 - Larry Pearlstein, Skyler Maxwell, Alex Aved:
Adaptive prediction resolution video coding for reduced DRAM bandwidth. 382-394 - Fabrizio Riente, Andrea Giordano, Marco Vacca, Mariagrazia Graziano:
Exploring N3ASIC technology for microwave imaging architectures. 395-405
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