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ORCIDIntegration, Volume 64
Volume 64, January 2019
- Anushree Mahapatra
, Benjamin Carrión Schäfer:
VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration. 1-12 - Tengfei Wang, Wei Guo, Jizeng Wei:
Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves. 13-21 - Hesong Xu, Nicola Massari, Leonardo Gasparini, Alessio Meneghetti, Alessandro Tomasi:
A SPAD-based random number generator pixel based on the arrival time of photons. 22-28 - Heechun Park, Taewhan Kim:
Hybrid asynchronous circuit generation amenable to conventional EDA flow. 29-39 - Xin-Yu Shih, Hong-Ru Chou:
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. 40-49 - Abderrazak Arabi, Nacerdine Bourouba, Abdesslam Belaout, Mouloud Ayad:
An accurate classifier based on adaptive neuro-fuzzy and features selection techniques for fault classification in analog circuits. 50-59 - Muhammed Ceylan Morgül, Mustafa Altun:
Optimal and heuristic algorithms to synthesize lattices of four-terminal switches. 60-70 - Raffaele De Rose, Paul Romero, Marco Lanuzza:
Double-precision Dual Mode Logic carry-save multiplier. 71-77 - Eric Schneider, Hans-Joachim Wunderlich:
Multi-level timing and fault simulation on GPUs. 78-91 - Trio Adiono, Khilda Afifah, Suksmandhira Harimurti, Prasetiyo, Amy Hamidah Salman:
Fully integrated transceiver module with a temperature compensation for high bit rate contactless smart card. 92-104 - Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones:
Yielding optimized dependability assurance through bit inversion. 105-113 - Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti:
A study of analog decision feedback equalization for ADC-Based serial link receivers. 114-126 - Sri Harsha Gade, Shobha Sundar Ram, Sujay Deb:
Millimeter wave wireless interconnects in deep submicron chips: Challenges and opportunities. 127-136 - Rasoul Moradi, Ebrahim Farshidi, Mohammad Soroosh:
A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer. 137-142 - Jiaji He, Xiaolong Guo, Travis Meade, Raj Gautam Dutta, Yiqiang Zhao, Yier Jin:
SoC interconnection protection through formal verification. 143-151 - Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta:
Look-ahead mapping of Boolean functions in memristive crossbar array. 152-162 - Remigiusz Wisniewski, Grzegorz Bazydlo, Pawel Szczesniak:
SVM algorithm oriented for implementation in a low-cost Xilinx FPGA. 163-172 - Qingli Guo, Jing Ye, Bing Li, Yu Hu, Xiaowei Li, Yazhu Lan, Guohe Zhang:
PUFPass: A password management mechanism based on software/hardware codesign. 173-183 - Soraya Aghnout, Gholamreza Karimi:
Modeling triplet spike timing dependent plasticity using a hybrid TFT-memristor neuromorphic synapse. 184-191
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