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Jwu E. Chen
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Journal Articles
- 2023
- [j20]Chung-Huang Yeh
, Jwu E. Chen:
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments. IEEE Des. Test 40(3): 45-52 (2023) - [j19]Chung-Huang Yeh
, Jwu E. Chen:
Multiple Retest Systems for Screening High-Quality Chips. J. Electron. Test. 39(2): 207-225 (2023) - [j18]Chung-Huang Yeh
, Jwu E. Chen:
Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method. J. Circuits Syst. Comput. 32(12): 2350202:1-2350202:20 (2023) - 2022
- [j17]Chung-Huang Yeh
, Jwu E. Chen:
Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect. Sensors 22(11): 4158 (2022) - 2019
- [j16]Chung-Huang Yeh
, Jwu E. Chen:
Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. J. Electron. Test. 35(4): 459-472 (2019) - 2009
- [j15]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 306-311 (2009) - 2007
- [j14]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23(4): 341-355 (2007) - [j13]Katherine Shu-Min Li, Yao-Wen Chang
, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1625-1636 (2007) - 2006
- [j12]Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang
, Chung-Len Lee, Jwu E. Chen:
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2513-2525 (2006) - 2003
- [j11]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003) - 2002
- [j10]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. 18(6): 571-581 (2002) - 2001
- [j9]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. 17(6): 483-494 (2001) - 2000
- [j8]Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. 16(1-2): 147-155 (2000) - [j7]Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su:
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000) - 1999
- [j6]Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen:
A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15(6): 885-897 (1999) - 1998
- [j5]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998) - 1997
- [j4]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1025-1033 (1997) - 1995
- [j3]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. 12(3): 14-23 (1995) - 1991
- [j2]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. 2(4): 395-397 (1991) - [j1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1559-1568 (1991)
Conference and Workshop Papers
- 2021
- [c37]Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng
, Peter Yi-Yu Liao, Sying-Jyan Wang
, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS 2021: 1-2 - [c36]Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang
, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC 2021: 208-212 - 2020
- [c35]Ken Chau-Cheung Cheng
, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang
, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen:
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE 2020: 1710-1711 - [c34]Chung-Huang Yeh
, Jwu E. Chen:
The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing. ITC-Asia 2020: 88-93 - [c33]Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng
, Katherine Shu-Min Li, Sying-Jyan Wang
, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang:
Innovative Practice on Wafer Test Innovations. VTS 2020: 1 - 2006
- [c32]Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 - [c31]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8 - 2005
- [c30]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187 - [c29]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229 - [c28]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329 - [c27]Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen:
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365 - [c26]Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 - 2004
- [c25]Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen:
A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium 2004: 58-61 - [c24]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150 - 2002
- [c23]Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen:
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium 2002: 170-175 - [c22]Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen:
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE 2002: 1119 - 2001
- [c21]Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen:
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. Asian Test Symposium 2001: 151-156 - 2000
- [c20]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30 - [c19]Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su:
A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95 - [c18]Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343 - [c17]Chin-Te Kao, Sam Wu, Jwu E. Chen:
A case study of failure analysis and guardband determination for a 64M-bit DRAM. Asian Test Symposium 2000: 447- - 1999
- [c16]Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen:
A DFT for semi-DC fault diagnosis for switched-capacitor circuits. ETW 1999: 58-63 - 1998
- [c15]Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen:
Maximization of power dissipation under random excitation for burn-in testing. ITC 1998: 567-576 - [c14]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347 - 1997
- [c13]Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen:
Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288- - [c12]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273 - 1996
- [c11]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15 - [c10]Jwu E. Chen:
Yield Improvement by Test Error Cancellation. Asian Test Symposium 1996: 258-262 - 1995
- [c9]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen:
Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39 - [c8]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229- - [c7]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Factorization of Multi-Valued Logic Functions. ISMVL 1995: 164-169 - 1994
- [c6]Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee:
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC 1994: 508-512 - [c5]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin:
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661 - [c4]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL 1994: 44-51 - [c3]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Complete Test Set for Multiple-Valued Logic Networks. ISMVL 1994: 289-296 - 1992
- [c2]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL 1992: 181-188 - 1990
- [c1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault collapsing analysis in sequential logic circuits. ITC 1990: 809-814
Coauthor Index
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