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ORCIDJohn Keane 0001
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
- affiliation (PhD 2010): University of Minnesota, Minneapolis, MN, USA
Other persons with the same name
- John Keane — disambiguation page
- John Keane 0002 (aka: John Eric Keane) — Rutgers University, NJ, USA
- John Keane 0003 — Norkom Technologies
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Journal Articles
- 2017
[j16]Jaydeep P. Kulkarni
, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52(1): 229-239 (2017)- 2016
- [j15]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang:
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. IEEE J. Solid State Circuits 51(1): 222-229 (2016) - 2014
- [j14]Xiaofei Wang, John Keane, Tony Tae-Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim:
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. IEEE Micro 34(6): 74-85 (2014) - 2013
- [j13]Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr:
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. IEEE J. Solid State Circuits 48(1): 150-158 (2013) - 2012
- [j12]John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar:
Process and Reliability Sensors for Nanoscale CMOS. IEEE Des. Test Comput. 29(5): 8-17 (2012) - 2011
- [j11]John Keane, Wei Zhang, Chris H. Kim:
An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. IEEE J. Solid State Circuits 46(10): 2374-2385 (2011) - [j10]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 787-795 (2011) - 2010
- [j9]John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim:
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. IEEE J. Solid State Circuits 45(4): 817-829 (2010) - [j8]John Keane, Tony Tae-Hyoung Kim, Xiaofei Wang, Chris H. Kim:
On-chip reliability monitors for measuring circuit degradation. Microelectron. Reliab. 50(8): 1039-1053 (2010) - [j7]John Keane, Tony Tae-Hyoung Kim, Chris H. Kim:
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 947-956 (2010) - 2009
- [j6]Jie Gu, John Keane, Chris H. Kim:
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 128-136 (2009) - [j5]Jie Gu, Hanyong Eom, John Keane, Chris H. Kim:
Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1203-1211 (2009) - 2008
- [j4]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. IEEE J. Solid State Circuits 43(2): 518-529 (2008) - [j3]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 206-209 (2008) - [j2]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 598-602 (2008) - 2007
- [j1]Tony Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim:
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 821-829 (2007)
Conference and Workshop Papers
- 2016
- [c14]John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC 2016: 308-309 - 2015
- [c13]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang:
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ISSCC 2015: 1-3 - [c12]Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang:
A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. VLSIC 2015: 266- - 2014
- [c11]Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim:
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. CICC 2014: 1-4 - 2012
- [c10]Pulkit Jain, John Keane, Chris H. Kim:
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. ESSDERC 2012: 262-265 - 2008
- [c9]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC 2008: 121-124 - [c8]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
Circuit techniques for ultra-low power subthreshold SRAMs. ISCAS 2008: 2574-2577 - [c7]Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim:
A multi-story power delivery technique for 3D integrated circuits. ISLPED 2008: 57-62 - 2007
- [c6]John Keane, Tony Tae-Hyoung Kim, Chris H. Kim:
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ISLPED 2007: 189-194 - [c5]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. ISSCC 2007: 330-606 - 2006
- [c4]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Width Quantization Aware FinFET Circuit Design. CICC 2006: 337-340 - [c3]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428 - [c2]Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim:
Utilizing reverse short channel effect for optimal subthreshold circuit design. ISLPED 2006: 127-130 - [c1]Jie Gu, John Keane, Chris H. Kim:
Modeling and analysis of leakage induced damping effect in low voltage LSIs. ISLPED 2006: 382-387
Coauthor Index
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