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ORCIDJie Han 0001
Person information
- affiliation: University of Alberta, Department of Electrical and Computer Engineering, Edmonton, AB, Canada
- affiliation (former): Northeastern University, Department of Electrical and Computer Engineering, Boston, MA, USA
- affiliation (former): Florida University, Department of Electrical and Computer Engineering, Advanced Computing and Information Systems Laboratory, Gainesville, FL, USA
- affiliation (PhD 2004): Delft University of Technology, The Netherlands
Other persons with the same name
- Jie Han — disambiguation page
- Jie Han 0002
![[0000-0002-2013-2962]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-2013-2962")
— Beijing Institute of Technology, School of Mathematics and Statistics, China (and 3 more) - Jie Han 0003 — King Abdullah University of Science and Technology, Jeddah, Saudi Arabia
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Journal Articles
- 2024
[j94]Shaowei Wang, Guangjun Xie, Wenbing Xu, Yongqiang Zhang, Jie Han:
A Low-Cost and Fault-Tolerant Stochastic Architecture for the Bernsen Algorithm Using Bitstream Correlation. J. Circuits Syst. Comput. 33(9) (2024)- [j93]Hai Mo, Yong Wu, Honglan Jiang, Zining Ma, Fabrizio Lombardi, Jie Han, Leibo Liu:
Learning the Error Features of Approximate Multipliers for Neural Network Applications. IEEE Trans. Computers 73(3): 842-856 (2024) - [j92]Zijing Niu, Tingting Zhang, Honglan Jiang, Bruce F. Cockburn, Leibo Liu, Jie Han:
Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 209-222 (2024) - [j91]Yongqiang Zhang, Xiaoyue Chen, Jie Han, Guangjun Xie:
Stochastic Mean Circuits Based on Inner-Product Units Using Correlated Bitstreams. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 867-871 (2024) - [j90]Ying Wu, Chuangtao Chen, Weihua Xiao, Xuan Wang, Chenyi Wen, Jie Han, Xunzhao Yin, Weikang Qian, Cheng Zhuo:
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits. ACM Trans. Design Autom. Electr. Syst. 29(1): 23:1-23:37 (2024) - [j89]Yongqiang Zhang, Jiao Qin, Jie Han, Guangjun Xie:
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 442-454 (2024) - 2023
- [j88]Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40(3): 5-7 (2023) - [j87]Qichao Tao, Tingting Zhang, Jie Han:
An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems. IEEE Embed. Syst. Lett. 15(4): 226-229 (2023) - [j86]Paul P. Sotiriadis, Jie Han, M. Hassan Najafi, Josep Lluís Rosselló Sanz:
Guest Editorial Unconventional Computing Techniques for Emerging Technology Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 1-6 (2023) - [j85]Xuemei Fan, Tingting Zhang, Hao Liu, Shengli Lu, Jie Han:
A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 237-248 (2023) - [j84]Tong Li, Honglan Jiang, Hai Mo, Jie Han, Leibo Liu, Zhi-Gang Mao:
Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators. J. Comput. Sci. Technol. 38(2): 309-327 (2023) - [j83]Yongqiang Zhang, Lingyun Xie, Jie Han, Xin Cheng, Guangjun Xie:
Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 771-775 (2023) - [j82]Yongqiang Zhang, Siting Liu, Jie Han, Zhendong Lin, Shaowei Wang, Xin Cheng, Guangjun Xie:
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1439-1443 (2023) - 2022
- [j81]Shaowei Wang, Guangjun Xie, Jie Han, Yongqiang Zhang:
Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing. Int. J. Circuit Theory Appl. 50(4): 1375-1385 (2022) - [j80]Wenbing Xu, Guangjun Xie, Shaowei Wang, Zhendong Lin, Jie Han, Yongqiang Zhang:
A stochastic computing architecture for local contrast and mean image thresholding algorithm. Int. J. Circuit Theory Appl. 50(9): 3279-3291 (2022) - [j79]Mario Barbareschi, Salvatore Barone, Alberto Bosio, Jie Han, Marcello Traiola:
A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(3): 50:1-50:25 (2022) - [j78]Yong Wu, Honglan Jiang, Zining Ma, Pengfei Gou, Yong Lu, Jie Han, Shouyi Yin, Shaojun Wei, Leibo Liu:
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2655-2668 (2022) - [j77]Francisco Javier Hernandez Santiago, Honglan Jiang, Hussam Amrouch, Andreas Gerstlauer, Leibo Liu, Jie Han:
Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4558-4571 (2022) - [j76]Mohammad Saeed Ansari, Bruce F. Cockburn, Jie Han:
Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications. IEEE Trans. Emerg. Top. Comput. 10(1): 500-506 (2022) - [j75]Haroon Waris, Chenghua Wang, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers. IEEE Trans. Emerg. Top. Comput. 10(1): 507-513 (2022) - 2021
- [j74]Mohammad Saeed Ansari, Shyama Gandhi, Bruce F. Cockburn, Jie Han:
Fast and low-power leading-one detectors for energy-efficient logarithmic computing. IET Comput. Digit. Tech. 15(4): 241-250 (2021) - [j73]Mohammad Saeed Ansari, Bruce F. Cockburn, Jie Han:
An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing. IEEE Trans. Computers 70(4): 614-625 (2021) - [j72]Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Shouyi Yin, Shaojun Wei, Leibo Liu:
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2170-2183 (2021) - [j71]Tian Yuan, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 250-263 (2021) - [j70]Honglan Jiang, Shaahin Angizi, Deliang Fan, Jie Han, Leibo Liu:
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1217-1230 (2021) - [j69]Zhendong Lin, Guangjun Xie, Wenbing Xu, Jie Han, Yongqiang Zhang:
Accelerating Stochastic Computing Using Deterministic Halton Sequences. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3351-3355 (2021) - [j68]Shanshan Liu, Pedro Reviriego, Jing Guo, Jie Han, Fabrizio Lombardi:
Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design. IEEE Trans. Emerg. Top. Comput. 9(4): 2064-2075 (2021) - [j67]Yidong Liu, Siting Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han:
A Survey of Stochastic Computing Neural Networks for Machine Learning Applications. IEEE Trans. Neural Networks Learn. Syst. 32(7): 2809-2824 (2021) - 2020
- [j66]Morgan Ledwon, Bruce F. Cockburn, Jie Han:
High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis. IEEE Access 8: 62207-62217 (2020) - [j65]Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei:
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. 52(6): 118:1-118:39 (2020) - [j64]Yuying Zhu, Weiqiang Liu, Peipei Yin, Tian Cao, Jie Han, Fabrizio Lombardi:
Design, evaluation and application of approximate-truncated Booth multipliers. IET Circuits Devices Syst. 14(8): 1305-1317 (2020) - [j63]Yongqiang Zhang, Guangjun Xie, Jie Han:
A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata. Microprocess. Microsystems 74: 103033 (2020) - [j62]Honglan Jiang, Francisco Javier Hernandez Santiago, Hai Mo, Leibo Liu, Jie Han:
Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications. Proc. IEEE 108(12): 2108-2135 (2020) - [j61]Sanbao Su, Chen Zou, Weijiang Kong, Jie Han, Weikang Qian:
A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 654-669 (2020) - [j60]Yibo Wu, Leibo Liu, Liang Wang, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei:
Aggressive Fine-Grained Power Gating of NoC Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3177-3189 (2020) - [j59]Ke Chen, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
Profile-Based Output Error Compensation for Approximate Arithmetic Circuits. IEEE Trans. Circuits Syst. 67-I(12): 4707-4718 (2020) - [j58]Liang Wang, Leibo Liu, Jie Han, Xiaohang Wang, Shouyi Yin, Shaojun Wei:
Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. IEEE Trans. Parallel Distributed Syst. 31(3): 611-622 (2020) - [j57]Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han:
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 317-328 (2020) - 2019
- [j56]Yongqiang Zhang, Guangjun Xie, Jie Han:
Serial concatenated convolutional code encoder in quantum-dot cellular automata. Nano Commun. Networks 22 (2019) - [j55]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation. IEEE Trans. Computers 68(11): 1635-1646 (2019) - [j54]Liang Wang, Ping Lv, Leibo Liu, Jie Han, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak:
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1771-1784 (2019) - [j53]Honglan Jiang, Cong Liu, Fabrizio Lombardi, Jie Han:
Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 189-202 (2019) - [j52]Honglan Jiang, Leibo Liu, Pieter P. Jonker, Duncan G. Elliott, Fabrizio Lombardi, Jie Han:
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 313-326 (2019) - [j51]Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2213-2221 (2019) - 2018
- [j50]Peican Zhu, Xiaogang Song, Leibo Liu, Zhen Wang, Jie Han:
Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation. IEEE Access 6: 35292-35304 (2018) - [j49]Mohammad Saeed Ansari, Honglan Jiang, Bruce F. Cockburn, Jie Han:
Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 404-416 (2018) - [j48]Yidong Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han:
An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 454-465 (2018) - [j47]Xiaogang Song, Zhengjun Zhai, Yidong Liu, Jie Han:
A stochastic approach for the reliability evaluation of multi-state systems with dependent components. Reliab. Eng. Syst. Saf. 170: 257-266 (2018) - [j46]Yidong Liu, Siting Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han:
A Stochastic Computational Multi-Layer Perceptron with Backward Propagation. IEEE Trans. Computers 67(9): 1273-1286 (2018) - [j45]Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana, Witold Pedrycz:
Automatic Selection of Process Corner Simulations for Faster Design Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1312-1316 (2018) - [j44]Siting Liu, Honglan Jiang, Leibo Liu, Jie Han:
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2530-2541 (2018) - [j43]Linbin Chen, Jie Han, Weiqiang Liu, Paolo Montuschi, Fabrizio Lombardi:
Design, Evaluation and Application of Approximate High-Radix Dividers. IEEE Trans. Multi Scale Comput. Syst. 4(3): 299-312 (2018) - [j42]Siting Liu, Jie Han:
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1326-1339 (2018) - [j41]Yan Li, Yufeng Li, Jie Han, Jianhao Hu, Fan Yang, Xuan Zeng, Bruce F. Cockburn, Jie Chen:
Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1585-1589 (2018) - [j40]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han:
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2572-2576 (2018) - 2017
- [j39]Xiaogang Song, Zhengjun Zhai, Peican Zhu, Jie Han:
A Stochastic Computational Approach for the Analysis of Fuzzy Systems. IEEE Access 5: 13465-13477 (2017) - [j38]Peican Zhu, Yangming Guo, Fabrizio Lombardi, Jie Han:
Approximate reliability of multi-state two-terminal networks by stochastic analysis. IET Networks 6(5): 116-124 (2017) - [j37]Honglan Jiang, Cong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(4): 60:1-60:34 (2017) - [j36]Ke Chen, Jie Han, Fabrizio Lombardi:
Two Approximate Voting Schemes for Reliable Computing. IEEE Trans. Computers 66(7): 1227-1239 (2017) - [j35]Weiqiang Liu, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, Fabrizio Lombardi:
Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing. IEEE Trans. Computers 66(8): 1435-1441 (2017) - [j34]Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC). IEEE Trans. Multi Scale Comput. Syst. 3(3): 139-151 (2017) - [j33]Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei:
A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. IEEE Trans. Parallel Distributed Syst. 28(3): 662-676 (2017) - 2016
- [j32]Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. Integr. 52: 156-167 (2016) - [j31]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Design, evaluation and fault-tolerance analysis of stochastic FIR filters. Microelectron. Reliab. 57: 111-127 (2016) - [j30]Peican Zhu, Jie Han, Yangming Guo, Fabrizio Lombardi:
Reliability and Criticality Analysis of Communication Networks by Stochastic Computation. IEEE Netw. 30(6): 70-76 (2016) - [j29]Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
On the Design of Approximate Restoring Dividers for Error-Tolerant Applications. IEEE Trans. Computers 65(8): 2522-2533 (2016) - [j28]Honglan Jiang, Jie Han, Fei Qiao, Fabrizio Lombardi:
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation. IEEE Trans. Computers 65(8): 2638-2644 (2016) - [j27]Peican Zhu, Jie Han, Leibo Liu, Fabrizio Lombardi:
Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation. IEEE Trans. Reliab. 65(3): 1612-1623 (2016) - [j26]Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 521-529 (2016) - [j25]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3169-3183 (2016) - 2015
- [j24]Chen Wu, Chenchen Deng, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei:
Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints. Sci. China Inf. Sci. 58(8): 1-14 (2015) - [j23]Amir Momeni, Jie Han, Paolo Montuschi, Fabrizio Lombardi:
Design and Analysis of Approximate Compressors for Multiplication. IEEE Trans. Computers 64(4): 984-994 (2015) - [j22]Cong Liu, Jie Han, Fabrizio Lombardi:
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders. IEEE Trans. Computers 64(5): 1268-1281 (2015) - [j21]Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei:
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8): 1264-1277 (2015) - [j20]Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory. IEEE Trans. Multi Scale Comput. Syst. 1(3): 127-137 (2015) - [j19]Peican Zhu, Jie Han, Leibo Liu, Fabrizio Lombardi:
A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures. IEEE Trans. Reliab. 64(3): 878-892 (2015) - [j18]Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei:
Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. ACM Trans. Reconfigurable Technol. Syst. 8(3): 19:1-19:24 (2015) - [j17]Ke Chen, Jie Han, Fabrizio Lombardi:
On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1160-1164 (2015) - [j16]Jie Han, Eugene Leung, Leibo Liu, Fabrizio Lombardi:
A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1562-1566 (2015) - [j15]Leibo Liu, Chen Wu, Chenchen Deng, Shouyi Yin, Qinghua Wu, Jie Han, Shaojun Wei:
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2566-2580 (2015) - [j14]Ke Chen, Jie Han, Fabrizio Lombardi:
On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2695-2699 (2015) - 2014
- [j13]Peican Zhu, Jinghang Liang, Jie Han:
Gene perturbation and intervention in context-sensitive stochastic Boolean networks. BMC Syst. Biol. 8: 60 (2014) - [j12]Peican Zhu, Jie Han:
Asynchronous Stochastic Boolean Networks as Gene Network Models. J. Comput. Biol. 21(10): 771-783 (2014) - [j11]Wei Wei, Jie Han, Fabrizio Lombardi:
Robust HSPICE modeling of a single electron turnstile. Microelectron. J. 45(4): 394-407 (2014) - [j10]Peican Zhu, Jie Han:
Stochastic Multiple-Valued Gene Networks. IEEE Trans. Biomed. Circuits Syst. 8(1): 42-53 (2014) - [j9]Jie Han, Hao Chen, Jinghang Liang, Peican Zhu, Zhixi Yang, Fabrizio Lombardi:
A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation. IEEE Trans. Computers 63(6): 1336-1350 (2014) - [j8]Peican Zhu, Jie Han, Leibo Liu, Ming Jian Zuo:
A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates. IEEE Trans. Reliab. 63(2): 480-494 (2014) - 2013
- [j7]Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Qinghua Wu, Shaojun Wei:
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration. J. Syst. Archit. 59(7): 482-491 (2013) - [j6]Jinghang Liang, Jie Han, Fabrizio Lombardi:
Analysis of Error Masking and Restoring Properties of Sequential Circuits. IEEE Trans. Computers 62(9): 1694-1704 (2013) - [j5]Jinghang Liang, Jie Han, Fabrizio Lombardi:
New Metrics for the Reliability of Approximate and Probabilistic Adders. IEEE Trans. Computers 62(9): 1760-1771 (2013) - [j4]Jinghang Liang, Zhiyin Zhou, Jie Han, Duncan G. Elliott:
A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 108-115 (2013) - 2012
- [j3]Jinghang Liang, Jie Han:
Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks. BMC Syst. Biol. 6: 113 (2012) - 2011
- [j2]Jie Han, Hao Chen, Erin Boykin, José A. B. Fortes:
Reliability evaluation of logic circuits using probabilistic gate models. Microelectron. Reliab. 51(2): 468-476 (2011) - 2005
- [j1]Jie Han, Jianbo Gao, Yan Qi, Pieter Jonker, José A. B. Fortes:
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. IEEE Des. Test Comput. 22(4): 328-339 (2005)
Conference and Workshop Papers
- 2024
- [c87]Wenhui Zhang, Xinkuang Geng, Qin Wang, Jie Han, Honglan Jiang:
A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System. ACM Great Lakes Symposium on VLSI 2024: 125-131 - 2023
- [c86]Pengyue Hou, Jie Han, Xingyu Li:
Improving Adversarial Robustness with Self-Paced Hard-Class Pair Reweighting. AAAI 2023: 14883-14891 - [c85]Chengcheng Tang, Jie Han:
Hardware Efficient Weight-Binarized Spiking Neural Networks. DATE 2023: 1-6 - 2022
- [c84]Qichao Tao, Jie Han:
Solving traveling salesman problems via a parallel fully connected ising machine. DAC 2022: 1123-1128 - [c83]Tingting Zhang, Jie Han:
Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation. DATE 2022: 548-551 - [c82]Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu:
Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. HPCA 2022: 986-1000 - [c81]Pengyue Hou, Ming Zhou, Jie Han, Petr Musílek, Xingyu Li:
Adversarial Fine-tune with Dynamically Regulated Adversary. IJCNN 2022: 1-8 - [c80]Tingting Zhang, Qichao Tao, Bailiang Liu, Jie Han:
A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization. ISCAS 2022: 1877-1881 - [c79]Tingting Zhang, Zijing Niu, Jie Han:
A Brief Review of Logarithmic Multiplier Designs. LATS 2022: 1-4 - 2021
- [c78]Zijing Niu, Honglan Jiang, Mohammad Saeed Ansari, Bruce F. Cockburn, Leibo Liu, Jie Han:
A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks. ACM Great Lakes Symposium on VLSI 2021: 65-70 - [c77]Tingting Zhang, Qichao Tao, Jie Han:
Solving Traveling Salesman Problems Using Ising Models with Simulated Bifurcation. ISOCC 2021: 288-289 - [c76]Zhendong Lin, Guangjun Xie, Shaowei Wang, Jie Han, Yongqiang Zhang:
A Review of Deterministic Approaches to Stochastic Computing. NANOARCH 2021: 1-6 - [c75]Yuancheng Zhou, Guangjun Xie, Jie Han, Yongqiang Zhang:
Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing. NANOARCH 2021: 1-6 - [c74]Chengcheng Tang, Jie Han:
Design and Implementation of a Highly Accurate Stochastic Spiking Neural Network. SiPS 2021: 1-6 - 2020
- [c73]Liang Wang, Leibo Liu, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei:
CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology. DAC 2020: 1-6 - [c72]Siting Liu, Jie Han:
Dynamic Stochastic Computing for Digital Signal Processing Applications. DATE 2020: 604-609 - 2019
- [c71]Shyama Gandhi, Mohammad Saeed Ansari, Bruce F. Cockburn, Jie Han:
Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier. CCECE 2019: 1-4 - [c70]Morgan Ledwon, Bruce F. Cockburn, Jie Han:
Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression. CCECE 2019: 1-6 - [c69]Mohammad Saeed Ansari, Bruce F. Cockburn, Jie Han:
A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy. DATE 2019: 928-931 - [c68]Honglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han:
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. ACM Great Lakes Symposium on VLSI 2019: 393-398 - [c67]Ruizhe Cai, Ao Ren, Olivia Chen, Ning Liu, Caiwen Ding, Xuehai Qian, Jie Han, Wenhui Luo, Nobuyuki Yoshikawa, Yanzhi Wang:
A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology. ISCA 2019: 567-578 - [c66]Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao:
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. ISVLSI 2019: 111-115 - [c65]Tingting Zhang, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders. NANOARCH 2019: 1-6 - 2018
- [c64]Yidong Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han:
An energy-efficient stochastic computational deep belief network. DATE 2018: 1175-1178 - [c63]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. DATE 2018: 1411-1416 - [c62]Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin, Ronald F. DeMara, Deliang Fan:
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks. ACM Great Lakes Symposium on VLSI 2018: 397-402 - [c61]Xuedi Wang, Zhe Chen, Kaige Jia, Jie Han, Qi Wei, Fei Qiao, Huazhong Yang:
Approximate On-chip Memory Optimization Method For Deep Residual Networks. DSP 2018: 1-5 - [c60]Ke Chen, Jie Han, Paolo Montuschi, Weiqiang Liu, Fabrizio Lombardi:
Design and Application of an Approximate 2-D Convolver with Error Compensation. ISCAS 2018: 1-5 - [c59]Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, Jingtong Hu, Yanzhi Wang:
An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing. ISQED 2018: 314-321 - [c58]Yuying Zhu, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
A Probabilistic Error Model and Framework for Approximate Booth Multipliers. NANOARCH 2018: 7-12 - [c57]Jie Han:
Approximate Arithmetic Circuits and Their Applications. NOCS 2018: 22:1 - 2017
- [c56]Honglan Jiang, Leibo Liu, Jie Han:
An efficient hardware design for cerebellar models using approximate circuits: special session paper. CODES+ISSS 2017: 31:1-31:2 - [c55]Siting Liu, Jie Han:
Hardware ODE Solvers using Stochastic Circuits. DAC 2017: 81:1-81:6 - [c54]Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao:
A true random number generator based on parallel STT-MTJs. DATE 2017: 606-609 - [c53]Siting Liu, Jie Han:
Energy efficient stochastic computing with Sobol sequences. DATE 2017: 650-653 - [c52]Yuanchang Chen, Yizhe Zhu, Fei Qiao, Jie Han, Yuansheng Liu, Huazhong Yang:
Evaluating Data Resilience in CNNs from an Approximate Memory Perspective. ACM Great Lakes Symposium on VLSI 2017: 89-94 - [c51]Linbin Chen, Fabrizio Lombardi, Paolo Montuschi, Jie Han, Weiqiang Liu:
Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition. ACM Great Lakes Symposium on VLSI 2017: 293-298 - [c50]Ke Chen, Fabrizio Lombardi, Jie Han:
Partially universal modules for high performance logic circuit design. MWSCAS 2017: 108-111 - [c49]Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
Design and operational assessment of an intra-cell hybrid L2 cache. NANOARCH 2017: 1-6 - 2016
- [c48]Mohammad Saeed Ansari, Ali Mahani, Jie Han, Bruce F. Cockburn:
A novel gate grading approach for soft error tolerance in combinational circuits. CCECE 2016: 1-4 - [c47]Ke Chen, Fabrizio Lombardi, Jie Han:
Design and analysis of an approximate 2D convolver. DFT 2016: 31-34 - [c46]Salin Junsangsri, Jie Han, Fabrizio Lombardi:
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File. ACM Great Lakes Symposium on VLSI 2016: 21-26 - [c45]Manish Rana, Ramon Canal, Jie Han, Bruce F. Cockburn:
SRAM memory margin probability failure estimation using Gaussian Process regression. ICCD 2016: 448-451 - [c44]Liangyu Qian, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi, Jie Han:
Design and evaluation of an approximate Wallace-Booth multiplier. ISCAS 2016: 1974-1977 - [c43]Honglan Jiang, Chengkun Shen, Pieter P. Jonker, Fabrizio Lombardi, Jie Han:
Adaptive Filter Design Using Stochastic Circuits. ISVLSI 2016: 122-127 - [c42]Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei, Huazhong Yang:
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis. ISVLSI 2016: 385-390 - [c41]Honglan Jiang, Cong Liu, Naman Maheshwari, Fabrizio Lombardi, Jie Han:
A comparative evaluation of approximate multipliers. NANOARCH 2016: 191-196 - [c40]Linbin Chen, Fabrizio Lombardi, Jie Han, Weiqiang Liu:
A fully parallel approximate CORDIC design. NANOARCH 2016: 197-202 - [c39]Jie Han:
Introduction to approximate computing. VTS 2016: 1 - 2015
- [c38]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Stochastic circuit design and performance evaluation of vector quantization. ASAP 2015: 111-115 - [c37]Chen Zou, Weikang Qian, Jie Han:
DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis. ASICON 2015: 1-4 - [c36]Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, Jie Han:
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. ASP-DAC 2015: 48-53 - [c35]Michael Shoniker, Bruce F. Cockburn, Jie Han, Witold Pedrycz:
Minimizing the number of process corner simulations during design verification. DATE 2015: 289-292 - [c34]Ke Chen, Fabrizio Lombardi, Jie Han:
An approximate voting scheme for reliable computing. DATE 2015: 293-296 - [c33]Salin Junsangsri, Fabrizio Lombardi, Jie Han:
Evaluating the impact of spike and flicker noise in phase change memories. DFTS 2015: 1-6 - [c32]Zhixi Yang, Jie Han, Fabrizio Lombardi:
Approximate compressors for error-resilient multiplier design. DFTS 2015: 183-186 - [c31]Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing. ACM Great Lakes Symposium on VLSI 2015: 51-56 - [c30]Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM). ACM Great Lakes Symposium on VLSI 2015: 259-264 - [c29]Honglan Jiang, Jie Han, Fabrizio Lombardi:
A Comparative Review and Evaluation of Approximate Adders. ACM Great Lakes Symposium on VLSI 2015: 343-348 - [c28]Zhixi Yang, Jie Han, Fabrizio Lombardi:
Transmission gate-based approximate adders for inexact computing. NANOARCH 2015: 145-150 - [c27]Ke Chen, Fabrizio Lombardi, Jie Han:
Matrix multiplication by an inexact systolic array. NANOARCH 2015: 151-156 - [c26]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Design and evaluation of stochastic FIR filters. PACRIM 2015: 407-412 - [c25]Naman Maheshwari, Zhixi Yang, Jie Han, Fabrizio Lombardi:
A Design Approach for Compressor Based Approximate Multipliers. VLSID 2015: 209-214 - 2014
- [c24]Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction. DATE 2014: 1-4 - [c23]Cong Liu, Jie Han, Fabrizio Lombardi:
A low-power, high-performance approximate multiplier with configurable partial error recovery. DATE 2014: 1-4 - [c22]Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
A system-level scheme for resistance drift tolerance of a multilevel phase change memory. DFT 2014: 63-68 - [c21]Linbin Chen, Fabrizio Lombardi, Jie Han:
FDSOI SRAM cells for low power design at 22nm technology node. MWSCAS 2014: 527-530 - [c20]Linbin Chen, Fabrizio Lombardi, Jie Han:
An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior. MWSCAS 2014: 993-996 - [c19]Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A memristor-based TCAM (Ternary Content Addressable Memory) cell. NANOARCH 2014: 1-6 - [c18]Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design. NANOARCH 2014: 45-50 - 2013
- [c17]Jie Han, Michael Orshansky:
Approximate computing: An emerging paradigm for energy-efficient design. ETS 2013: 1-6 - [c16]Yu Ren, Leibo Liu, Shouyi Yin, Qinghua Wu, Shaojun Wei, Jie Han:
A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. ISCAS 2013: 1793-1796 - [c15]Hao Wu, Fabrizio Lombardi, Jie Han:
A PCM-based TCAM cell using NDR. NANOARCH 2013: 89-94 - 2012
- [c14]Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han:
Hardening a memory cell for low power operation by gate leakage reduction. DFT 2012: 73-78 - [c13]Fabrizio Lombardi, Wei Wei, Jie Han:
Modeling a single electron turnstile in HSPICE. ACM Great Lakes Symposium on VLSI 2012: 221-226 - [c12]Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
Macromodeling a phase change memory (PCM) cell by HSPICE. NANOARCH 2012: 77-84 - [c11]Jinghang Liang, Jie Han, Linbin Chen, Fabrizio Lombardi:
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. NANOARCH 2012: 131-138 - [c10]Vikas Sakode, Fabrizio Lombardi, Jie Han:
Cell design and comparative evaluation of a novel 1T memristor-based memory. NANOARCH 2012: 152-159 - 2011
- [c9]Jinghang Liang, Jie Han, Fabrizio Lombardi:
On the Reliable Performance of Sequential Adders for Soft Computing. DFT 2011: 3-10 - [c8]Hao Chen, Jie Han, Fabrizio Lombardi:
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits. DFT 2011: 60-67 - [c7]Nachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han, Fabrizio Lombardi:
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS. DFT 2011: 309-315 - [c6]Wei Wei, Jie Han, Fabrizio Lombardi:
A hybrid memory cell using Single-Electron transfer. NANOARCH 2011: 16-23 - 2010
- [c5]Hao Chen, Jie Han:
Stochastic computational models for accurate reliability evaluation of logic circuits. ACM Great Lakes Symposium on VLSI 2010: 61-66 - 2005
- [c4]Jie Han, Erin Taylor, Jianbo Gao, José A. B. Fortes:
Faults, Error Bounds and Reliability of Nanoelectronic Circuits. ASAP 2005: 247-253 - 2004
- [c3]Jie Han, Pieter Jonker:
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers. ICPR (3) 2004: 2-7 - 2003
- [c2]Jie Han, Pieter Jonker:
A Study on Fault-Tolerant Circuits Using Redundancy. VLSI 2003: 65-69 - 2000
- [c1]Pieter Jonker, Jie Han:
On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits. CAMP 2000: 69-
Parts in Books or Collections
- 2022
- [p3]Tingting Zhang, Honglan Jiang, Weiqiang Liu, Fabrizio Lombardi, Leibo Liu, Seok-Bum Ko, Jie Han:
Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications. Approximate Computing 2022: 119-146 - [p2]Hao Zhang, Mohammadreza Asadikouhanjani, Jie Han, Deivalakshmi Subbian, Seok-Bum Ko:
Approximate Computing for Efficient Neural Network Computation: A Survey. Approximate Computing 2022: 397-427 - 2019
- [p1]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Approximate Arithmetic Circuits: Design and Evaluation. Approximate Circuits 2019: 67-98
Editorship
- 2022
- [e3]Christof Teuscher, Jie Han:
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, NANOARCH 2022, Virtual, OR, USA, December 7-9, 2022. ACM 2022, ISBN 978-1-4503-9938-8 [contents] - 2017
- [e2]Laleh Behjat, Jie Han, Miroslav N. Velev, Deming Chen:
Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017. ACM 2017, ISBN 978-1-4503-4972-7 [contents] - 2016
- [e1]Ayse K. Coskun, Martin Margala, Laleh Behjat, Jie Han:
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. ACM 2016, ISBN 978-1-4503-4274-2 [contents]
Informal and Other Publications
- 2023
- [i6]Ying Wu, Chuangtao Chen, Weihua Xiao, Xuan Wang, Chenyi Wen, Jie Han, Xunzhao Yin, Weikang Qian, Cheng Zhuo:
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits. CoRR abs/2301.12181 (2023) - 2022
- [i5]Pengyue Hou, Ming Zhou, Jie Han, Petr Musílek, Xingyu Li:
Adversarial Fine-tune with Dynamically Regulated Adversary. CoRR abs/2204.13232 (2022) - [i4]Pengyue Hou, Jie Han, Xingyu Li:
Improving Adversarial Robustness with Self-Paced Hard-Class Pair Reweighting. CoRR abs/2210.15068 (2022) - 2021
- [i3]Haichao Yu, Zhe Chen, Dong Lin, Gil I. Shamir, Jie Han:
Dropout Prediction Variation Estimation Using Neuron Activation Strength. CoRR abs/2110.06435 (2021) - 2019
- [i2]Ruizhe Cai, Ao Ren, Olivia Chen, Ning Liu, Caiwen Ding, Xuehai Qian, Jie Han, Wenhui Luo, Nobuyuki Yoshikawa, Yanzhi Wang:
A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology. CoRR abs/1907.09077 (2019) - 2018
- [i1]Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, Jingtong Hu, Yanzhi Wang:
An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional Neural Networks using Stochastic Computing. CoRR abs/1802.01016 (2018)
Coauthor Index
[j93] [j75] [j71] [j68] [j67] [j64] [j59] [j55] [j53] [j52] [j51] [j48] [j46] [j43] [j38] [j37] [j36] [j35] [j34] [j32] [j30] [j29] [j28] [j27] [j26] [j23] [j22] [j20] [j19] [j17] [j16] [j14] [j11] [j9] [j6] [j5] [c68] [c65] [c64] [c63] [c60] [c58] [c51] [c50] [c49] [c47] [c46] [c44] [c43] [c41] [c40] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [p3] [p1]
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