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ORCID26th ASAP 2015: Toronto, ON, Canada
- 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2015, Toronto, ON, Canada, July 27-29, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-1925-3
- Arvind:
BlueDBM: A multi-access, distributed flash store for Big Data analytics. - Derek Chiou:
Accelerating data centers with reconfigurable logic. - Cecilia González-Alvarez, Jennifer B. Sartor, Carlos Álvarez
, Daniel Jiménez-González, Lieven Eeckhout:
Automatic design of domain-specific instructions for low-power processors. 1-8 - Nachiket Kapre:
Custom FPGA-based soft-processors for sparse graph acceleration. 9-16 - Raphael Polig, Heiner Giefers, Walter Stechele:
A soft-core processor array for relational operators. 17-24 - Nasim Farahini, Ahmed Hemani:
Atomic stream computation unit based on micro-thread level parallelism. 25-29 - Tanvir Ahmed, Yuko Hara-Azumi:
Timing speculation-aware instruction set extension for resource-constrained embedded systems. 30-34 - Nolan Denman, Mandana Amiri, Kevin Bandura, Liam Connor, Matt Dobbs, Mateus Fandino, Mark Halpern, Adam D. Hincks, Gary Hinshaw, Carolin Höfer, Peter Klages, Kiyoshi Masui, Juan Mena Parra, Laura Newburgh, Andre Recnik, J. Richard Shaw, Kris Sigurdson, Kendrick Smith, Keith Vanderlinde:
A GPU-based correlator X-engine implemented on the CHIME Pathfinder. 35-40 - Nitin A. Gawande, Joseph B. Manzano, Antonino Tumeo, Nathan R. Tallent, Darren J. Kerbyson, Adolfy Hoisie:
Power and performance trade-offs for Space Time Adaptive Processing. 41-48 - Tahsin Reza, Aaron Zimmer, Parwant Ghuman, Tanuj kr Aasawat, Matei Ripeanu:
Accelerating persistent scatterer pixel selection for InSAR processing. 49-56 - Andre Recnik, Kevin Bandura, Nolan Denman, Adam D. Hincks, Gary Hinshaw, Peter Klages, Ue-Li Pen, Keith Vanderlinde:
An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine. 57-61 - S. Ross Thompson, James E. Stine:
An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers. 62-63 - Wei He, Dirmanto Jap:
Dual-rail active protection system against side-channel analysis in FPGAs. 64-65 - Tung Thanh Hoang, Amirali Shambayati, Henry Hoffmann, Andrew A. Chien:
Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators. 66-67 - Bingzhe Li, M. Hassan Najafi, David J. Lilja:
An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. 68-69 - Mehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski:
Application-set driven exploration for custom processor architectures. 70-71 - Abdelhamid Dine, Abdelhafid Elouardi, Bastien Vincke, Samir Bouaziz:
Speeding up graph-based SLAM algorithm: A GPU-based heterogeneous architecture study. 72-73 - Hugues de Lassus Saint-Genies, David Defour, Guillaume Revy:
Range reduction based on Pythagorean triples for trigonometric function evaluation. 74-81 - Yongchao Liu, Bertil Schmidt:
LightSpMV: Faster CSR-based sparse matrix-vector multiplication on CUDA-enabled GPUs. 82-89 - Ran Zheng, Wei Wang, Hai Jin, Song Wu, Yong Chen, Han Jiang:
GPU-based multifrontal optimizing method in sparse Cholesky factorization. 90-97 - Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A metamorphotic Network-on-Chip for various types of parallel applications. 98-105 - Ming-Ju Wu, Yan-Ting Chen, Chun-Jen Tsai:
Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors. 106-110 - Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Stochastic circuit design and performance evaluation of vector quantization. 111-115 - Glenn E. R. Cowan, Kevin Cushon, Warren J. Gross:
Mixed-signal implementation of differential decoding using binary message passing algorithms. 116-119 - Mihai Maruseac, Gabriel Ghinita, Ming Ouyang, Razvan Rughinis:
Hardware acceleration of Private Information Retrieval protocols using GPUs. 120-127 - Moon Sung Lee, Yongje Lee, Jung Hee Cheon, Yunheung Paek:
Accelerating bootstrapping in FHEW using GPUs. 128-135 - Tedy Thomas, Arman Pouraghily, Kekai Hu, Russell Tessier, Tilman Wolf:
Multi-task support for security-enabled embedded processors. 136-143 - Pei Luo, Liwei Zhang, Yunsi Fei, A. Adam Ding:
Towards secure cryptographic software implementation against side-channel power analysis attacks. 144-148 - Paulo Martins, Leonel Sousa, Julien Eynard, Jean-Claude Bajard:
Programmable RNS lattice-based parallel cryptographic decryption. 149-153 - Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser:
Balance power leakage to fight against side-channel analysis at gate level in FPGAs. 154-155 - Jie Tang, Chen Liu, Jean-Luc Gaudiot:
How can Garbage Collection be energy efficient by dynamic offloading? 156-157 - Zhinan Cheng, Xi Li, Beilei Sun, Ce Gao, Jiachen Song:
Automatic frame rate-based DVFS of game. 158-159 - Rodrigo Devigo, Liana Dessandre Duenha, Rodolfo Azevedo, Ricardo Santos:
MultiExplorer: A tool set for multicore system-on-chip design exploration. 160-161 - Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Noxim: An open, extensible and cycle-accurate network on chip simulator. 162-163 - Peter Klages, Kevin Bandura, Nolan Denman, Andre Recnik, Jonathan Sievers, Keith Vanderlinde:
GPU kernels for high-speed 4-bit astrophysical data processing. 164-165 - Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich:
Loop coarsening in C-based High-Level Synthesis. 166-173 - Dylan Rudolph, Greg Stitt:
An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems. 174-180 - Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney:
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. 181-188 - Kenneth Hill, Stefan Craciun, Alan D. George, Herman Lam:
Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA. 189-193 - Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari:
On-demand fault-tolerant loop processing on massively parallel processor arrays. 194-201 - Aniruddha Shastri, Greg Stitt, Eduardo Riccio:
A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications. 202-209 - Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon:
Reconfigurable acceleration of fitness evaluation in trading strategies. 210-217 - Hamed Tabkhi, Majid Sabbagh, Gunar Schirner:
An efficient architecture solution for low-power real-time background subtraction. 218-225 - Shijie Zhou, Yun Rock Qu, Viktor K. Prasanna:
Large-scale packet classification on FPGA. 226-233 - Andrew J. Wong, Saied Hemati, Warren J. Gross:
Efficient implementation of structured long block-length LDPC codes. 234-238
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