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"Design and reliability analysis of multiple valued logic gates using ..."

Jinghang Liang et al. (2012)

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DOI: 10.1145/2765491.2765515

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-11

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  dblp key:
  - conf/nanoarch/LiangHCL12
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  persistent URL:
  - https://dblp.org/rec/conf/nanoarch/LiangHCL12
Jinghang Liang, Jie Han, Linbin Chen, Fabrizio Lombardi:
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. NANOARCH 2012: 131-138

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