Volume 17, Number 1, January 1998
Volume 17, Number 2, February 1998
: Grid quality and its influence on accuracy and convergence in device simulation.
Steve H. Jen
, Bing J. Sheu
: A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs.
Volume 17, Number 3, March 1998
D. Michael Miller
: An improved method for computing a generalized spectral coefficient.
, Sudhakar M. Reddy
: Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
Volume 17, Number 4, April 1998
, Martin D. F. Wong
: Switch bound allocation for maximizing routability in timing-driven routing of FPGA's.
Volume 17, Number 5, May 1998
Kerry S. Lowe
, P. Glenn Gulak
: A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.
Vladimir B. Dmitriev-Zdorov
: Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation.
John F. Beetem
: Rebel: a clustering algorithm for look-up table FPGA's.
Volume 17, Number 6, June 1998
Volume 17, Number 7, July 1998
Volume 17, Number 8, August 1998
Volume 17, Number 9, September 1998
, Chang Wu
: An efficient algorithm for performance-optimal FPGA technology mapping with retiming.
Volume 17, Number 10, October 1998
Bharat P. Dave
, Niraj K. Jha
: COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems.
Robert P. Dick
, Niraj K. Jha
: MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems.
, Bernd Becker
: Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
Volume 17, Number 11, November 1998
Mahesh B. Patil
: New discretization scheme for two-dimensional semiconductor device simulation on triangular grid.
Radomir S. Stankovic
: Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices.
Volume 17, Number 12, December 1998
: Random pattern testability of memory address logic.