VTS 2004: Napa Valley, CA, USA

Defect-Oriented Testing

• Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer:
  Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. 9-15
  
• Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra:
  ELF-Murphy Data on Defects and Test Sets. 16-22
  
• Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo:
  An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. 23-30
  

Delay Testing

• Manish Sharma, Janak H. Patel:
  What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? 31-36
  
• Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi:
  A Statistical Fault Coverage Metric for Realistic Path Delay Faults. 37-42
  
• Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger:
  Delay Defect Screening using Process Monitor Structures. 43-52
  

Current Based Testing

• Josep Rius Vázquez, José Pineda de Gyvez:
  Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. 53-58
  
• Claude Thibeault:
  On New Current Signatures and Adaptive Test Technique Combination. 59-64
  
• Sagar S. Sabade, D. M. H. Walker:
  On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. 65-72
  

Test Data Compression and Low-Speed ATE

• Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams:
  Changing the Scan Enable during Shift. 73-78
  
• C. V. Krishna, Nur A. Touba:
  3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. 79-86
  
• Michael R. Nelms, Kevin Gorman, Darren Anand:
  Generating At-Speed Array Fail Maps with Low-Speed ATE. 87-96
  

Pattern Debug, Yield Analysis and FPGA Testing

• Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran:
  Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application. 97-102
  
• Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre:
  Yield Analysis of Logic Circuits. 103-108
  
• Erik Chmelar, Shahin Toutounchi:
  FPGA Bridging Fault Detection and Location via Differential I{DDQ}. 109-116
  

Memory Testing I

• Zaid Al-Ars, Said Hamdioui, A. J. van de Goor:
  Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. 117-122
  
• Mohamed Azimane, Ananta K. Majhi:
  New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. 123-128
  
• Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
  March iC-: An Improved Version of March C- for ADOFs Detection. 129-138
  

MEMs Testing and FPGA Testing

• Nilmoni Deb, R. D. (Shawn) Blanton:
  Multi-Modal Built-In Self-Test for Symmetric Microsystems. 139-147
  
• Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
  A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. 148-153
  
• Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure:
  A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. 154-170
  

Low-Voltage and Thermal Testing

• Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker:
  The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. 171-178
  
• Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov:
  Sensing temperature in CMOS circuits for Thermal Testing. 179-184
  
• Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware:
  Detection of Temperature Sensitive Defects Using ZTC. 185-192
  

Logic Built-In Self-Test

• Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
  Planar High Performance Ring Generators. 193-198
  
• Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
  Logic BIST Using Constrained Scan Cells. 199-205
  
• Salvador Manich, L. García, L. Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
  BIST Technique by Equally Spaced Test Vector Sequences. 206-216
  

Analog Testing I

• Sule Ozev, Christian Olgaard:
  Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures. 217-222
  
• Qi Wang, Yi Tang, Mani Soma:
  GHz RF Front-end Bandwidth Time Domain Measurement. 223-228
  
• Soumendu Bhattacharya, Ganesh Srinivasan, Sasikumar Cherubal, Achintya Halder, Abhijit Chatterjee:
  System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams. 229-236
  

Memory Testing II

• Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian:
  Reducing Embedded SRAM Test Time under Redundancy Constraints. 237-242
  
• Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk:
  Memory BIST Using ESP. 243-248
  
• Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
  A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. 249-260
  

Analog Testing II

• Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio:
  An On-Chip Transfer Function Characterization System for Analog Built-in Testing. 261-266
  
• Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
  A Scalable On-Chip Jitter Extraction Technique. 267-272
  
• Selim Sermet Akbay, Abhijit Chatterjee:
  Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference. 273-290
  

Defect Analysis and Fault Simulation

• Mehdi Baradaran Tahoori, Mariam Momenzadeh, Jing Huang, Fabrizio Lombardi:
  Defects and Faults in Quantum Cellular Automata at Nano Scale. 291-296
  
• Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton:
  Generalized Sensitization using Fault Tuples. 297-303
  
• Abhishek Singh, Chintan Patel, Jim Plusquellic:
  Fault Simulation Model for i{DDT} Testing: An Investigation. 304-312
  

Issues in Reliability

• Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
  A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. 313-318
  
• Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
  Cost-Driven Selection of Parity Trees. 319-324
  
• Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff:
  Soft Delay Error Effects in CMOS Combinational Circuits. 325-334
  

Wireless and System Testing

• Hans Eberle, Arvinderpal Wander, Nils Gura:
  Testing Systems Wirelessly. 335-340
  
• Brian Moore, Christopher J. Backhouse, Martin Margala:
  Design of Wireless Sub-Micron Characterization System. 341-346
  
• Tian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh:
  Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks. 347-354
  

System-on-Chip Testing

• Gang Zeng, Hideo Ito:
  Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. 355-360
  
• Erik Larsson, Julien Pouget, Zebo Peng:
  Defect-Aware SOC Test Scheduling. 361-366
  
• Md. Saffat Quasem, Sandeep K. Gupta:
  Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. 367-376
  

Analog Testing and Design Validation

• Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee:
  Prediction of Analog Performance Parameters Using Oscillation Based Test. 377-382
  
• Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
  An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. 383-388
  
• Qingwei Wu, Michael S. Hsiao:
  Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. 389-405
  

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