VTS 1998: Princeton, NJ, USA

Core and System on Chip Test

Testing Deep Submicron Circuits

Diagnosis and Validation

BIST 1

Scan & Boundary Scan

IDDQ and VLV Test

Analog Test

Sequential Test and Redundancy Removal

Embedded Tutorial 1

Delay Fault Test

BIST 2

Testing High-Speed Circuits

Validation/Verification

Defect Level Test

Concurrent Checking & Fault Tolerance

Panel 1

Panel and Embedded Tutorial 2

Embedded Tutorial 3

Scan Techniques

On-Line Testing

Analog/Mixed Signal Test and DFT

Memory Test

BIST 3

New ATPG Techniques

Panel 3

Embedded Tutorial 4

Panel 4