VTS 1998:
Princeton, NJ, USACore and System on Chip Test
export record as
dblp key:
conf/vts/KosonockyBWHKABHHIJJPRS98 Stephen V. Kosonocky ,
Arthur A. Bright ,
Kevin W. Warren ,
Ruud A. Haring ,
Steve Klepner ,
Sameh W. Asaad ,
S. Basavaiah ,
Bob Havreluk ,
David F. Heidel ,
Michael Immediato ,
Keith A. Jenkins ,
Rajiv V. Joshi ,
Benjamin D. Parker ,
T. V. Rajeevakumar ,
Kevin G. Stawiasz :
Designing a Testable System on a Chip.
2-7
export record as
dblp key:
Debashis Bhattacharya :
Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit.
8-14
export record as
dblp key:
Testing Deep Submicron Circuits
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Diagnosis and Validation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Pradip Bose :
Performance Test Case Generation for Microprocessors.
54-61
BIST 1
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Albrecht P. Stroele :
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions.
78-85
Scan & Boundary Scan
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
IDDQ and VLV Test
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Analog Test
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Sequential Test and Redundancy Removal
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Embedded Tutorial 1
export record as
dblp key:
Pinaki Mazumder :
Analysis of Failures in Deep Submicron SRAM Cells.
184-187
Delay Fault Test
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
BIST 2
export record as
dblp key:
conf/vts/ParthasarathyB98 export record as
dblp key:
export record as
dblp key:
Jacob Savir :
Distributed Generation of Weighted Random Patterns.
225-233
Testing High-Speed Circuits
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Validation/Verification
export record as
dblp key:
export record as
dblp key:
Li-C. Wang ,
Magdy S. Abadir ,
Jing Zeng :
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
260-265
export record as
dblp key:
Defect Level Test
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Concurrent Checking & Fault Tolerance
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel 1
export record as
dblp key:
Panel and Embedded Tutorial 2
export record as
dblp key:
Embedded Tutorial 3
export record as
dblp key:
Scan Techniques
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
On-Line Testing
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Arsen Kuchukyan :
Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check.
362-369
Analog/Mixed Signal Test and DFT
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Memory Test
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
BIST 3
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
New ATPG Techniques
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel 3
export record as
dblp key:
Embedded Tutorial 4
export record as
dblp key:
Panel 4
export record as
dblp key:
data released under the ODC-BY 1.0 license
