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ORCIDSameh W. Asaad
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2020 – today
- 2024
[c19]Yuan Ma, Scott Smith, Bill Gropp, Hubertus Franke, Bharat Sukhwani, Sameh W. Asaad, Jinjun Xiong, Volodymyr V. Kindratenko, Deming Chen:
UniNet: Accelerating the Container Network Data Plane in IaaS Clouds. CLOUD 2024: 115-127- 2023
- [c18]Bharat Sukhwani
, Mohit Kapur, Alda Ohmacht, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes, Sameh W. Asaad:
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation. FPGA 2023: 230 - [c17]Benjamin Reidys, Yuqi Xue, Daixuan Li, Bharat Sukhwani, Wen-Mei Hwu, Deming Chen, Sameh W. Asaad, Jian Huang:
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design. SOSP 2023: 182-199 - [i1]Benjamin Reidys, Yuqi Xue, Daixuan Li, Bharat Sukhwani, Wen-mei W. Hwu, Deming Chen, Sameh W. Asaad, Jian Huang:
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design. CoRR abs/2309.06513 (2023)
2010 – 2019
- 2017
- [c16]Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad:
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. MICRO 2017: 15-26 - 2016
- [c15]Dajung Lee, Roger Moussalli, Sameh W. Asaad, Mudhakar Srivatsa:
Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware. FCCM 2016: 176-183 - 2015
- [j5]Bharat Sukhwani, Mathew Thoennes, Hong Min, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger:
A Hardware/Software Approach for Database Query Acceleration with FPGAs. Int. J. Parallel Program. 43(6): 1129-1159 (2015) - [c14]Roger Moussalli, Mudhakar Srivatsa, Sameh W. Asaad:
Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates. FCCM 2015: 179-186 - 2014
- [j4]Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger:
Database Analytics: A Reconfigurable-Computing Approach. IEEE Micro 34(1): 19-29 (2014) - [j3]Lok-Won Kim, Sameh W. Asaad, Ralph Linsker:
A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network. ACM Trans. Reconfigurable Technol. Syst. 7(1): 5:1-5:23 (2014) - [c13]Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha:
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC 2014: 27-38 - 2013
- [c12]Robert J. Halstead, Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Sameh W. Asaad, Balakrishna Iyer:
Accelerating Join Operation for Relational Databases with FPGAs. FCCM 2013: 17-20 - [c11]Roger Moussalli, Bharat Sukhwani, Sameh W. Asaad:
FINPAGE: Generating high performance feed-specific parser circuits. GlobalSIP 2013: 1132 - [c10]Bharat Sukhwani, Mathew Thoennes, Hong Min, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger:
Large Payload Streaming Database Sort and Projection on FPGAs. SBAC-PAD 2013: 25-32 - 2012
- [c9]Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Balakrishna Iyer, Bernard Brezzo, Donna Dillenberger, Sameh W. Asaad:
Database analytics acceleration using FPGAs. PACT 2012: 411-420 - [c8]Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno:
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. FPGA 2012: 153-162 - [c7]Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad:
Efficient in-system RTL verification and debugging using FPGAs (abstract only). FPGA 2012: 269 - 2011
- [c6]Bharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad:
High-Throughput, Lossless Data Compresion on FPGAs. FCCM 2011: 113-116
2000 – 2009
- 2004
- [c5]Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno:
Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452 - 2003
- [j2]Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter:
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47(2-3): 299-326 (2003) - [c4]Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325 - 2000
- [j1]Ted Bapty, Sandeep Neema, Jason Scott, Janos Sztipanovits, Sameh W. Asaad:
Model-integrated Tools for the Design of Dynamically Reconfigurable Systems. VLSI Design 10(3): 281-306 (2000)
1990 – 1999
- 1998
- [c3]Sameh W. Asaad, Kevin W. Warren:
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. FPL 1998: 278-287 - [c2]Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz:
Designing a Testable System on a Chip. VTS 1998: 2-7 - 1996
- [c1]Koichi Suzumori, Sameh W. Asaad:
A novel pneumatic rubber actuator for mobile robot bases. IROS 1996: 1001-1006
Coauthor Index
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