ITC 1993:
Baltimore, MD, USAPlenary
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System Testing
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Colin Maunder :
A Universal Framework for Managed Built-in Test.
21-29
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I-DDQ And Logic Testing of CMOS Bridging
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Eugeni Isern ,
Joan Figueras :
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.
73-82
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SPC-Based Intelligent Test
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Kurt A. Milne :
Automated Wafer Lot Approval: A Statistically Based Implementation.
92-98
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Brian Beck :
Practical Application of Statistical Process Control in Semiconductor Manufacturing.
99-107
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Advancement In Test Generation
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Tom Austin :
Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development.
125-132
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Tony Taylor :
Tools and Techniques for Converting Simulation Models into Test Patterns.
133-138
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IEEE STD 1149.1 In Action
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Tom Langford :
Utilizing Boundary Scan to Implement BIST.
167-173
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Software Testability
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Cost-Effective Application Of Ate
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Delay Testing - Self Test
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Panel:
IEEE STD 1149.1:
Barriers - Real and Irrational!
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Colin Maunder :
Position Statement: ITC93 Boundary-Scan Panel.
262
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Panel:
Known Good Die:
A Key To Cost Effective MCMs
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Panel:
DFT - Profit Or Loss?
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Jon Turino :
DFT: Profit or Loss -- A Position Paper.
269
Panel:
Software Testing Got You Down?
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How Can CMOS IC Quality Be Improved?
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Rick Gayle :
The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage.
285-292
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Paul C. Wiscombe :
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels.
293-299
Testability Structures For Mixed-Signal Board Testing
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On-Product Bist
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Multichip Module Testing
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Lynn Roszel :
MCM Foundry Test Methodology and Implementation.
369-372
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DFT:
Putting Principles Into Practice
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Cary Champlin :
IRIDIUMtm Satellite: A Large System Application of Design for Testability.
392-398
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Rodham E. Tulloss :
IEEE 1149 Standards - Changing Testing, Silicon to Systems.
399-408
Making Test Generation Faster
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Mitsuo Teramoto :
A Method for Reducing the Search Space in Test Pattern Generation.
429-435
Test Engineering Strategies I
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Rudy Garcia :
Keep Alive - A New Requirement for High Performance uProcessor Test.
446-450
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conf/itc/BouwmeesterOBSTB93
Test Data Management
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Jim Mosley III :
A Flexible Approach to Data Collection for Component Test Systems.
461-470
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John O'Donnell :
Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs.
471-477
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DFT:
Winning It With Partial Scan
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IEEE STD 1149.1 Design Issues
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Lee Whetsel :
Hierarchically Accessing 1149.1 Applications in a System Environment.
517-526
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Timing Systems - Analysis And Time Measurement
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Richard K. Feldman :
A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems.
544-551
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Will Creek :
Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics.
556-565
Realistic Quality Practices
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Mani Soma :
Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers.
566-573
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Panel:
Mixed-Signal Test Bus:
Has It Arrived?
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Nai-Chi Lee :
Practical Considerations for Mixed-Signal Test Bus.
591-592
Panel:
Test Synthesis:
Fact Or Fiction?
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Panel:
Fault Coverage Numbers:
What Do They Really Mean?
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Constrained Test Generation
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conf/itc/KonijnenburgLG93 export record as
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conf/itc/VishakantaiahAS93 export record as
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Novel And Practical Power Supply Current Test Techniques
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Board Test:
Analog, Bare Board, Digital
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Christophe Vaucher ,
Louis Balme :
The Standard Mirror Boards (SMBs) Concept - An Innovative Improvement of Traditional ATE for up to 10 Mil Bare Board Testing.
672-679
Mixed Signal Device Test Techniques
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Compact Delay Testing
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Synthesis And Testability
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Microprocessor And VLSI Testing Case Studies
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conf/itc/BonnenbergCFKZF93
Design-For-Test Considerations For Mixed-Signal Devices
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conf/itc/TeraokaKYIMWSST93 export record as
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Memory Test
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Software Testing Methods
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Detection Of Physical Defects
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Udo Mahlstedt ,
Jürgen Alt :
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -.
883-892
Test Engineering Strategies II
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Selected Topics In Test
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Delay Testing
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Udo Mahlstedt :
DELTEST: Deterministic Test Generation for Gate-Delay Faults.
972-980
DFT:
New Tricks Of The Old Trade
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BIST Pattern Generation
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Michael Bershteyn :
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing.
1031-1040
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1992 Best Paper
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Robert C. Aitken :
BP-1992 A Comparison of Defect Models for Fault Location with IDDQ Measurements.
1051-1060
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