Tutorials

• 
  K. Maitra: Tutorial 1: The Promise of High-Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications. 3
• 
  Chris H. Kim: Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. 4
• 
  Robert E. Jones: Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology. 5
• 
  Subhasish Mitra: Tutorial 4: Robust System Design in Scaled CMOS. 6
• 
  Hillary Hunter: Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve? 7
• 
  Praveen Elakkumanan: Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM). 8-9

Plenary Session

• 
  Drew Gude: Plenary Speech 1P1: Shrinking time-to-market through global value chain integration. 15
• 
  Robert Hum: Plenary Speech 1P2: Bounding the Endless Verification Loop. 16-17

Power Conscious Memories

• 
  Mark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell: A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS. 23-29
• 
  Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar: Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation. 30-34
• 
  Maurizio Skerlj, Paolo Ienne: Error Protected Data Bus Inversion Using Standard DRAM Components. 35-42
• 
  Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas: Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. 43-46

Speed-Up and Timing of Integrated Circuits

• 
  Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis: Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. 47-52
• 
  Vineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. 53-56
• 
  Xin Wang, Alireza Kasnavi, Harold Levy: An Efficient Method for Fast Delay and SI Calculation Using Current Source Models. 57-61
• 
  Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai: Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model. 62-67

SER and Noise Tolerance

• 
  Avijit Dutta, Abhijit Jas: Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. 68-73
• 
  Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang: Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths. 74-77
• 
  Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen: IR Drop Reduction via a Flip-Flop Resynthesis Technique. 78-83
• 
  Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson: Noise Interaction Between Power Distribution Grids and Substrate. 84-89

Luncheon Keynote Speech

• 
  Antun Domic: Luncheon Keynote Speech. 90-91

Robust SRAM and Analog Circuits

• 
  Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran: Fundamental Data Retention Limits in SRAM Standby Experimental Results. 92-97
• 
  Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. 98-102
• 
  Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham: Cache Design for Low Power and High Yield. 103-107
• 
  Xin Li, Yu Cao: Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations. 108-113
• 
  Tian Xia, Stephen Wyatt: High Output Resistance and Wide Swing Voltage Charge Pump Circuit. 114-117

Power and Thermal Management

• 
  Krishnan Sundaresan, Nihar R. Mahapatra: Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. 118-122
• 
  Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula: A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. 123-126
• 
  Joseph F. Ryan, Benton H. Calhoun: Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. 127-132
• 
  Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. 133-136
• 
  Shervin Sharifi, Chunchen Liu, Tajana Simunic Rosing: Accurate Temperature Estimation for Efficient Thermal Management. 137-142

Process Variations

• 
  Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. 143-147
• 
  Seyed-Abdollah Aftabjahani, Linda S. Milor: Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. 148-151
• 
  Lei Zhang, Zhiping Yu, Xiangqing He: A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors. 152-155
• 
  Lin Xie, Azadeh Davoodi: Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. 156-161
• 
  Shubhankar Basu, Balaji Kommineni, Ranga Vemuri: Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. 162-167

System and Circuit Synthesis

• 
  Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk: High-Quality Circuit Synthesis for Modern Technologies. 168-173
• 
  Saraju P. Mohanty: ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. 174-177
• 
  Hwisung Jung, Massoud Pedram: Improving the Efficiency of Power Management Techniques by Using Bayesian Classification. 178-183
• 
  Jason D. Lee, Nikhil Gupta, Praveen Bhojwani, Rabi N. Mahapatra: An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. 184-189
• 
  Hyunok Oh: Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior. 190-193

Process, Characterization, and Temperature-Aware Design

• 
  Yu Zhong, Martin D. F. Wong: Thermal-Aware IR Drop Analysis in Large Power Grid. 194-199
• 
  Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta: A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. 200-206
• 
  Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev: Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. 207-212
• 
  Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda: Characterization of Standard Cells for Intra-Cell Mismatch Variations. 213-219
• 
  Tao Li, Zhiping Yu: Full-Chip Leakage Verification for Manufacturing Considering Process Variations. 220-223

Processor Test Verification / Delay Diagnosis

• 
  Sangeetha Sudhakrishnan, Liying Su, Jose Renau: Processor Verification with hwBugHunt. 224-229
• 
  Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi: Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. 230-235
• 
  Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram: Efficient Selection of Observation Points for Functional Tests. 236-241
• 
  Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas: A Novel Test Generation Methodology for Adaptive Diagnosis. 242-245
• 
  Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. 246-253

Embedded Technical Sessions

• 
  Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. 257-260
• 
  Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. 261-266
• 
  Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen: A Statistic-Based Approach to Testability Analysis. 267-270
• 
  Feng Liu, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, Mansun Chan: Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes. 271-276
• 
  Tsu-Shuan Chang, Manish Kumar, Teng-Sheng Moh, Chung-Li Tseng: On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem. 277-282
• 
  John Ferguson, Robert Todd: Architecting for Physical Verification Performance and Scaling. 283-288
• 
  Haixia Yan, Qiang Zhou, Xianlong Hong: Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. 289-292
• 
  Neehar Jandhyala, Lili He, Morris Jones: CMOS Based Low Cost Temperature Sensor. 293-296
• 
  Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar: An SSO Based Methodology for EM Emission Estimation from SoCs. 297-300
• 
  Muzhou Shao: Fast Timing Update under the Effect of IR Drop. 301-304
• 
  Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun: Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. 305-310
• 
  Sherif A. Tawfik, Volkan Kursun: Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. 311-316
• 
  Ricky Yiu-kee Choi, Chi-Ying Tsui: A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. 317-320
• 
  Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. 321-324
• 
  Srinivasa R. S. T. G, Jandhyala Srivatsava, Narahari Tondamuthuru R: Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies. 325-329
• 
  Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. 330-333
• 
  C. R. Venugopal, Prasanth Soraiyur, Jagannath Rao: Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation. 334-337
• 
  Qing Su, Charles Chiang, Jamil Kawa: Hotspot Based Yield Prediction with Consideration of Correlations. 338-343
• 
  Maharaj Mukherjee, Kanad Chakraborty: A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications. 344-347
• 
  José Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo A. Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler: A Passive 915 MHz UHF RFID Tag. 348-351
• 
  Jae-Seok Yang, Andrew R. Neureuther: Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. 352-356
• 
  Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong: DFM Based Detailed Routing Algorithm for ECP and CMP. 357-360
• 
  Toshinori Sato, Shingo Watanabe: Instruction Scheduling for Variation-Originated Variable Latencies. 361-364
• 
  Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo: Hotspot Prevention Using CMP Model in Design Implementation Flow. 365-368
• 
  Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo: The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era. 369-372
• 
  Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava: Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. 373-378
• 
  Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. 379-384
• 
  Charbel J. Akl, Magdy A. Bayoumi: Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. 385-390
• 
  Eric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. 391-395
• 
  Parastoo Nikaeen, Boris Murmann, Robert W. Dutton: Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs. 396-400
• 
  Vinay Jain, Payman Zarkesh-Ha: Analytical Noise-Rejection Model Based on Short Channel MOSFET. 401-406
• 
  Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas: A High-Performance Bus Architecture for Strongly Coupled Interconnects. 407-410
• 
  Zahra Sadat Ebadi, Resve A. Saleh: A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. 411-416
• 
  Alicia Strang, David Potts, Shankar Hemmady: A Holistic Approach to SoC Verification. 417-422
• 
  Nathaniel August: A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. 423-428
• 
  Jae Wook Kim, Boris Murmann, Robert W. Dutton: Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices. 429-432
• 
  Anil Deshpande: Verification of IP-Core Based SoC's. 433-436
• 
  Matthew G. Stout, Kenneth P. Tumin: Innovative Test Solutions for Pin-Limited Microcontrollers. 437-440
• 
  Ganesh R. Shamnur, Rajesh R. Berigei: XStatic: A Simulation Based ESD Verification and Debug Environment. 441-444
• 
  Sachin Shrivastava, Harindranath Parameswaran: Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping. 445-449
• 
  Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. 450-455
• 
  Paul Pao-Fang Cheng: A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models. 456-459
• 
  Ravi Surepeddi: System Verilog for Quality of Results (QoR). 460-464
• 
  Zhen Mu: Power Delivery System: Sufficiency, Efficiency, and Stability. 465-469
• 
  Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. 470-475
• 
  Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng: Clock Skew Analysis via Vector Fitting in Frequency Domain. 476-479
• 
  Sridhar Joshi, Ravi Perumal, Kamesh V. Gadepally, Mark Young: An Approach for a Comprehensive QA Methodology for the PDKs. 480-483
• 
  Kamesh V. Gadepally, Mark Young, James Lin, Andy Franklin, Ravi Perumal, Sridhar Joshi: Strategies for Quality CAD PDKs. 484-487
• 
  Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang: Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. 488-491
• 
  Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy: Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. 492-497
• 
  Rasit Onur Topaloglu: Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics. 498-501
• 
  Saurabh Sinha, Asha Balijepalli, Yu Cao: A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. 502-507
• 
  Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler: Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. 508-513
• 
  Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li: Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. 514-519
• 
  Shinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. 520-525
• 
  Sandeep Gupta, Jaya Singh, Abhijit Roy: A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs. 526-530
• 
  Yue Fu, Jin He, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang: Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure. 531-536
• 
  Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu: Elastic Timing Scheme for Energy-Efficient and Robust Performance. 537-542
• 
  Ning Lu: Statistical Models and Frequency-Dependent Corner Models for Passive Devices. 543-548
• 
  Enric Musoll: A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. 549-552
• 
  DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. 553-556
• 
  Salam D. Marougi: Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock. 557-563
• 
  David Matschulat, César A. M. Marcon, Fabiano Hessel: A QoS Scheduler for Real-Time Embedded Systems. 564-567
• 
  James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui: FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. 568-571
• 
  Jeff Mueller, Resve A. Saleh: A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. 572-577

Plenary Session

• 
  Sanjiv Taneja: Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test. 585
• 
  Chandu Visweswariah: Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality. 586
• 
  Rich Goldman: Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World. 587-588

Co-Design Applications for IC Packages

• 
  Anna Fontanelli: System-in-Package Technology: Opportunities and Challenges. 589-593
• 
  Thao Nguyen, Navid Rezvani: Printed Circuit Board Assembly Test Process and Design for Testability. 594-599
• 
  Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang: Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. 600-603
• 
  Ming-Fang Lai, Hung-Ming Chen: An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. 604-607
• 
  Santhosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam: Techniques for Early Package Closure in System-in-Packages. 608-613

Tools and Interconnects

• 
  Bo Yang, Shigetoshi Nakatake, Hiroshi Murata: Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. 617-620
• 
  Frank Liu, Peter Feldmann: MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis. 621-626
• 
  Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu: Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. 627-632

Sequential Analysis, Defect Modeling, and At-Speed Testing

• 
  Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas: Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. 633-636
• 
  Dan Zhu, Tun Li, Yang Guo, Sikun Li: 2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. 637-642
• 
  Jason G. Brown, R. D. (Shawn) Blanton: Automated Standard Cell Library Analysis for Improved Defect Modeling. 643-648
• 
  Ho Fai Ko, Nicola Nicolici: A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. 649-654

Modeling and Analysis in Physical Design

• 
  Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao: Finite-Point Gate Model for Fast Timing and Power Analysis. 657-662
• 
  Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. 663-669
• 
  Hai Lan, Ralf Schmitt, Chuck Yuan: Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces. 670-675
• 
  Anand Rajaram, Raguram Damodaran, Arjun Rajagopal: Practical Clock Tree Robustness Signoff Metrics. 676-679
• 
  Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Hierarchical Soft Error Estimation Tool (HSEET). 680-683

Emerging Technologies and Novel Applications

• 
  Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov: Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). 684-690
• 
  Arthur Nieuwoudt, Yehia Massoud: Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. 691-696
• 
  Rajat Subhra Chakraborty, Swarup Bhunia: Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. 697-701
• 
  Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif: Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. 702-707
• 
  Daniela De Venuto, Bruno Riccò: High Resolution Read-Out Circuit for DNA Label-Free Detection System. 708-711

Statistical Timing

• 
  Lin Xie, Azadeh Davoodi: Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. 712-717
• 
  Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng: Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. 718-723
• 
  Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise. 724-729
• 
  Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen: Process-Variation Statistical Modeling for VLSI Timing Analysis. 730-733
• 
  Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic: A Design Model for Random Process Variability. 734-737

Modern Processor Design

• 
  Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan: A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm. 738-743
• 
  Allen C. Cheng: Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform. 744-749
• 
  Kaiyu Chen, Sharad Malik, Priyadarsan Patra: Runtime Validation of Transactional Memory Systems. 750-756
• 
  Makoto Sugihara: SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. 757-762

Modeling and Design of Reliable Circuits

• 
  Wenping Wang, Shengqi Yang, Yu Cao: Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect. 763-768
• 
  Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu: An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. 769-773
• 
  Bin Zhang, Michael Orshansky: Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. 774-779
• 
  Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sarrafzadeh: Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems. 780-783
• 
  Görschwin Fey, Rolf Drechsler: A Basis for Formal Robustness Checking. 784-789

Design for Manufacturing

• 
  Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi: Quantified Impacts of Guardband Reduction on Design Process Outcomes. 790-797
• 
  Uthman Alsaiari, Resve A. Saleh: Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. 798-803
• 
  Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif: A Root-Finding Method for Assessing SRAM Stability. 804-809
• 
  Hailong Jiao, Lan Chen: Cellwise OPC Based on Reduced Standard Cell Library. 810-814
• 
  Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. 815-820

Structural Test

• 
  Anshuman Chandra, Rohit Kapur: Interval Based X-Masking for Scan Compression Architectures. 821-826
• 
  Stelios Neophytou, Maria K. Michael: Two New Methods for Accurate Test Set Relaxation via Test Set Replacement. 827-831
• 
  Adam B. Kinsman, Nicola Nicolici: Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. 832-837
• 
  Alodeep Sanyal, Sandip Kundu: A Built-in Test and Characterization Method for Circuit Marginality Related Failures. 838-843
• 
  Akhil Garg, Prashant Dubey: On Chip Jitter Measurement through a High Accuracy TDC. 844-847

Advanced Design Methodologies

• 
  Udo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael Pronath: Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas. 848-854
• 
  Sherif A. Tawfik, Volkan Kursun: Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. 855-860
• 
  Yu Zhou, Somnath Paul, Swarup Bhunia: Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. 861-866
• 
  Zuying Luo, Sheldon X.-D. Tan: Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method. 867-872
• 
  Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong: IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. 873-876

last updated on Wed May 22 02:55:23 2013 by the dblp team
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