ISQED 2008: San Jose, California, USA


Plenary Session

Power Conscious Memories

Speed-Up and Timing of Integrated Circuits

SER and Noise Tolerance

Luncheon Keynote Speech

Robust SRAM and Analog Circuits

Power and Thermal Management

Process Variations

System and Circuit Synthesis

Process, Characterization, and Temperature-Aware Design

Processor Test Verification / Delay Diagnosis

Embedded Technical Sessions

Plenary Session

Co-Design Applications for IC Packages

Tools and Interconnects

Sequential Analysis, Defect Modeling, and At-Speed Testing

Modeling and Analysis in Physical Design