ICCAD 2004: San Jose, California, USA
2004 International Conference on Computer-Aided Design (ICCAD'04), November 7-11, 2004, San Jose, CA, USA. IEEE Computer Society / ACM 2004 ISBN 0-7803-8702-3- Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi: Asymptotic probability extraction for non-normal distributions of circuit performance. 2-9
- Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. 10-13
- Debjit Sinha, Hai Zhou: Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. 14-19
- Jinfeng Liu, Pai H. Chou: Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization. 21-28
- Kihwan Choi, Wonbok Lee, Ramakrishna Soma, Massoud Pedram: Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation. 29-34
- Dakai Zhu, Rami G. Melhem, Daniel Mossé: The effects of energy management on reliability in real-time embedded systems. 35-40
- Andreas Kuehlmann: Dynamic transition relation simplification for bounded property checking. 50-57
- Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. 58-65
- Daniel Kroening, Edmund M. Clarke: Checking consistency of C and Verilog using predicate abstraction and induction. 66-72
- Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou: SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. 74-79
- Roland W. Freund: SPRIM: structure-preserving reduced-order interconnect macromodeling. 80-87
- Peter Feldmann, Frank Liu: Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. 88-92
- Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan: Fast simulation of VLSI interconnects. 93-98
- Quming Zhou, Kartik Mohanram: Cost-effective radiation hardening technique for combinational logic. 100-106
- Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. 107-110
- Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu: Banked scratch-pad memory management for reducing leakage energy consumption. 120-124
- Kimish Patel, Enrico Macii, Luca Benini, Massimo Poncino: Reducing cache misses by application-specific re-configurable indexing. 125-130
- Massimo Poncino, Jianwen Zhu: DynamoSim: a trace-based dynamically compiled instruction set simulator. 131-136
- Sani R. Nassif, Duane S. Boning, Nagib Hakim: The care and feeding of your statistical static timer. 138-139
- Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda: Analytical modeling of crosstalk noise waveforms using Weibull function. 141-146
- Igor Keller, Ken Tseng, Nishath K. Verghese: A robust cell-level crosstalk delay change analysis. 147-154
- Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda: Delay noise pessimism reduction by logic correlations. 160-167
- Anup Hosangadi, Farzan Fallah, Ryan Kastner: Factoring and eliminating common subexpressions in polynomial expressions. 169-174
- Markus Püschel, Adam C. Zelinski, James C. Hoe: Custom-optimized multiplierless implementations of DSP algorithms. 175-182
- Newton Cheung, Sri Parameswaran, Jörg Henkel: A quantitative study and estimation models for extensible instructions in embedded processors. 183-189
- André C. Nácul, Tony Givargis: Code partitioning for synthesis of embedded applications with phantom. 190-196
- Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni: Formal verification coverage: computing the coverage gap between temporal specifications. 198-203
- Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. 204-209
- Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar: Towards formal verification of analog designs. 210-217
- Young-Il Kim, Chong-Min Kyung: Automatic translation of behavioral testbench for fully accelerated simulation. 218-221
- Fei Su, Krishnendu Chakrabarty: Architectural-level synthesis of digital microfluidics-based biochips. 223-228
- Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan: Simultaneous design and placement of multiplexed chemical processing systems on microchips. 229-236
- Arijit Raychowdhury, Kaushik Roy: A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. 237-240
- Yehea I. Ismail, Chirayu S. Amin: Computation of signal threshold crossing times directly from higher order moments. 246-253
- Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Modeling unbuffered latches for timing analysis. 254-260
- Olivier Omedes, Michel Robert, Mohammed Ramdani: A flexibility aware budgeting for hierarchical flow timing closure. 261-266
- Ravishankar Rao, Sarma B. K. Vrudhula: Energy optimization for a two-device data flow chain. 268-274
- Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi: A power aware system level interconnect design methodology for latency-insensitive systems. 275-282
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the T-tree formulation. 300-305
- Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar: A chip-level electrostatic discharge simulation strategy. 315-318
- Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra: Efficient full-chip thermal modeling and analysis. 319-326
- Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron: Interconnect lifetime prediction under dynamic stress for reliability-aware design. 327-334
- Paul S. Zuchowski, Peter A. Habitz, J. D. Hayes, J. H. Oppold: Process and environmental variation impacts on ASIC timing. 336-342
- S. B. Samaan: The impact of device parameter variations on the frequency and performance of VLSI chips. 343-346
- Jingcao Hu, Radu Marculescu: Application-specific buffer space allocation for networks-on-chip router design. 354-361
- Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi: Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. 362-369
- Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic: Hardware/software managed scratchpad memory for embedded system. 370-377
- Aaron P. Hurst, Philip Chong, Andreas Kuehlmann: Physical placement driven by sequential timing analysis. 379-386
- Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-driven placement and white space allocation. 394-401
- Haoxing Ren, David Zhigang Pan, Paul Villarrubia: True crosstalk aware incremental placement with noise map. 402-409
- Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Variability inspired implementation selection problem. 423-427
- Seraj Ahmad, Rabi N. Mahapatra: M-trie: an efficient approach to on-chip logic minimization. 428-435
- Randal E. Bryant, Sriram K. Rajamani: Verifying properties of hardware and software by predicate abstraction and model checking. 437-438
- Frederic Worm, Paolo Ienne, Patrick Thiran: Soft self-synchronising codes for self-calibrating communication. 440-447
- Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo: SILENT: serialized low energy transmission coding for on-chip interconnection networks. 448-451
- James D. Ma, Rob A. Rutenbar: Interval-valued reduced order statistical interconnect modeling. 460-467
- Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. 468-472
- Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Efficient statistical timing analysis through error budgeting. 473-477
- Nestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis: Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates. 479-484
- Eli Chiprout: Fast flip-chip power grid analysis via locality and grid shells. 485-488
- Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik: HiSIM: hierarchical interconnect-centric circuit simulator. 489-496
- Vijay Durairaj, Priyank Kalla: Guiding CNF-SAT search via efficient constraint partitioning. 498-501
- Liang Zhang, Mukul R. Prasad, Michael S. Hsiao: Incremental deductive & inductive reasoning for SAT-based bounded model checking. 502-509
- Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. 510-517
- Feng Gao, John P. Hayes: Exact and heuristic approaches to input vector control for leakage power reduction. 527-532
- Vishal Khandelwal, Ankur Srivastava: Leakage control through fine-grained placement and sizing of sleep transistors. 533-536
- Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang: A vectorless estimation of maximum instantaneous current for sequential circuits. 537-540
- Satrajit Chatterjee, Robert K. Brayton: A new incremental placement algorithm and its application to congestion-aware divisor extraction. 541-548
- Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov: Unification of partitioning, placement and floorplanning. 550-557
- Andrew B. Kahng, Qinke Wang: An analytic placer for mixed-size placement and timing-driven placement. 565-572
- Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli: Engineering details of a stable force-directed placer. 573-580
- Yajun Ran, Malgorzata Marek-Sadowska: An integrated design flow for a via-configurable gate array. 582-589
- Nikhil Jayakumar, Sunil P. Khatri: A metal and via maskset programmable VLSI design methodology using PLAs. 590-594
- Renqiu Huang, Ranga Vemuri: Analysis and evaluation of a hybrid interconnect structure for FPGAs. 595-601
- Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: A yield improvement methodology using pre- and post-silicon statistical clock scheduling. 611-618
- A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: A novel clock distribution and dynamic de-skewing methodology. 626-631
- Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On per-test fault diagnosis using the X-fault model. 633-640
- Fang Liu, Sule Ozev, Martin A. Brooke: Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search. 641-647
- Chunsheng Liu: An efficient method for improving the quality of per-test fault diagnosis. 648-651
- Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh: A unified theory of timing budget management. 653-659
- Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Power estimation for cycle-accurate functional descriptions of hardware. 668-675
- Peng Li, Lawrence T. Pileggi: Efficient harmonic balance simulation using multi-level frequency decomposition. 677-682
- Xiaochun Duan, Kartikeya Mayaram: Frequency domain simulation of high-Q oscillators with homotopy methods. 683-686
- Xiaolue Lai, Jaijeet S. Roychowdhury: Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking. 687-694
- Chris Chu: FLUTE: fast lookup table based wirelength estimation technique. 696-701
- Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Wire-length prediction using statistical techniques. 702-705
- Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. 706-711
- Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng: A path-based methodology for post-silicon timing validation. 713-720
- Wenjing Rao, Alex Orailoglu, G. Su: Frugal linear network-based test decompression for drastic test cost reductions. 721-725
- Baris Arslan, Alex Orailoglu: Design space exploration for aggressive test cost reduction in CircularScan architectures. 726-731
- Bernd Koenemann: Design/process learning from electrical test. 733-738
- Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop: Backend CAD flows for "restrictive design rules". 739-746
- Maxim Teslenko, Elena Dubrova: Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth. 748-751
- Deming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. 752-759
- Lei He, Tulika Mitra, Weng-Fai Wong: Configuration bitstream compression for dynamically reconfigurable FPGAs. 766-773
- Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave: High-level synthesis: an essential ingredient for designing complex ASICs. 775-782
- Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: High-level synthesis using computation-unit integrated memories. 783-790
- Ajay K. Verma, Paolo Ienne: Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. 791-798
- Maged Ghoneima, Yehea I. Ismail: Formal derivation of optimal active shielding for low-power on-chip buses. 800-807
- Ashish Srivastava, Dennis Sylvester: A general framework for probabilistic low-power design space exploration considering process variation. 808-813
- Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing analysis considering spatial power/ground level variation. 814-820
- Muhammet Mustafa Ozdal, Martin D. F. Wong: Simultaneous escape routing and layer assignment for dense PCBs. 822-829
- Muhammet Mustafa Ozdal, Martin D. F. Wong: A provably good algorithm for high performance bus routing. 830-837
- Ryan Fung, Vaughn Betz, William Chow: Simultaneous short-path and long-path timing optimization for FPGAs. 838-845
- Guido Stehr, Helmut E. Graeb, Kurt Antreich: Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. 847-854
- Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi: Robust analog/RF circuit design with projection-based posynomial modeling. 855-862
- Jintae Kim, Jaeseo Lee, Lieven Vandenberghe: Techniques for improving the accuracy of geometric-programming based analog circuit design optimization. 863-870
- Joel R. Phillips: Variational interconnect analysis via PMTBR. 872-879
- Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula: Stochastic analysis of interconnect performance in the presence of process variations. 880-886
- Zhenhai Zhu, Jacob White, Alper Demir: A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. 887-891
- Daisuke Maruyama, Akira Kanuma, Takashi Mochiyama, Hiroaki Komatsu, Yaroku Sugiyama, Noriyuki Ito: Detection of multiple transitions in delay fault test of SPARC64 microprocessor. 893-898
- Erik Chmelar: Minimizing the number of test configurations for FPGAs. 899-902
- Feng Shi, Yiorgos Makris: SPIN-TEST: automatic test pattern generation for speed-independent circuits. 903-908
- A. Bernstein, M. Burton, Frank Ghenassia: How to bridge the abstraction gap in system level modeling and design. 910-914
- Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing software influences on substrate noise: an ADC perspective. 916-922
- F. De Bernarclinis, S. Gambini, R. Vincis, F. Svelto: Design space exploration for a UMTS front-end exploiting analog platforms. 923-930
- Ranga Vemuri, Glenn Wolfe: Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. 931-938
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last updated on 2013-06-19T201401 by the dblp team