ICCAD 1991: Santa Clara, California, USA

Physical Partitioning

Analog Simulation

Controller Synthesis


Interconnect Simulation


Module Generation

Numerical Algorithms

Topics in Logic Synthesis

Real World Framework Applications

Reliability and Manufacturability Analysis

Timing Analysis and Performance Optimization

Diagnostics and Testability Analysis

The False Path Problem in Timing Analysis

Encoding Algorithms

Built-In Self Test

Framework Directions

Techniques for Effective Memory Utilization

High-Level Layout Verification

Timing Analysis

Asynchronous Circuit Synthesis

Performance Driven and Parallel Routing Techniques

Topics in Simulation

Sequential Synthesis and Verification

Analog Circuit and Layout Synthesis

Scan Design

High-Level Synthesis - FSM Synthesis

Detailed Routing

Automatic Test Pattern Generation

Verification Algorithms

Transistor-Level Optimization and Layout

Design for Testability

Advances in Combinational Synthesis

Exact Algorithms in General Cell Routing

Fault Simulation

Synthesis for FPGA's

maintained by Schloss Dagstuhl LZI at University of Trier