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2000 – 2009
- 2008
[j8]Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa:
Delayed-ABC SOI for crosstalk noise repair. IEICE Electron. Express 5(9): 354-360 (2008)- [j7]Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto
, Masayuki Terai, Satoshi Kotani, Shigeo Sawada:
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3524-3530 (2008) - 2007
- [j6]Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai:
A Fast Characterizing Method for Large Embedded Memory Modules on SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 815-822 (2007) - 2005
- [j5]Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba:
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3463-3470 (2005)
1990 – 1999
- 1998
- [c9]Satoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki:
A CMOS cell generation system for two-dimensional transistor placement. CICC 1998: 325-328 - [c8]Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki:
A new router for reducing "antenna effect" in ASIC design. CICC 1998: 601-604 - 1995
- [j4]Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato:
Min-cut placement with global objective functions for large scale sea-of-gates arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 434-446 (1995) - 1994
- [j3]Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato:
A new approach to over-the-cell channel routing with three layers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 187-200 (1994) - [c7]Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato:
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays. ICCAD 1994: 428-431 - 1991
- [c6]Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato:
A New Model for Over-The-Cell Channel Routing with Three Layers. ICCAD 1991: 432-435 - 1990
- [c5]Masayuki Terai, Kazuhiro Takahashi, Koji Sato:
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint. DAC 1990: 96-102
1980 – 1989
- 1987
- [j2]Masayuki Terai, Yoshihide Ajioka, Tomoyoshi Noda, Masaru Ozaki, Tsunenori Umeki, Koji Sato:
Symbolic Layout System: Application Results and Functional Improvements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 346-354 (1987) - 1985
- [j1]Masayuki Terai:
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 329-336 (1985) - 1982
- [c4]Masayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara:
A consideration of the number of horizontal grids used in the routing of a masterslice layout. DAC 1982: 121-128 - 1981
- [c3]Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita:
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. DAC 1981: 59-65 - [c2]Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana:
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. DAC 1981: 812-819
1970 – 1979
- 1978
- [c1]Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita:
LORES - Logic Reorganization System. DAC 1978: 250-260
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