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Vijaya Sankara Rao Pasupureddi
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2020 – today
- 2024
- [j16]Srikanth Vuppunuthala
, Vijay Shankar Pasupureddi
:
3.6-pJ/Spike, 30-Hz Silicon Neuron Circuit in 0.5-V, 65-nm CMOS for Spiking Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2906-2910 (2024) - [j15]Rakesh Varma Rena
, Raviteja Kammari
, Vijay Shankar Pasupureddi
:
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 552-563 (2024) - [c33]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. ISCAS 2024: 1-5 - [c32]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS. ISCAS 2024: 1-5 - [c31]Perakalapudi Ravibabu, Prema Kumar Govindaswamy, Vijay Shankar Pasupureddi:
A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS. ISCAS 2024: 1-5 - [c30]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. ISQED 2024: 1-5 - [c29]Srinivasa Rao Maram, Subrahmanyam Boyapati, Vijay Shankar Pasupureddi:
A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology. ISQED 2024: 1-7 - 2023
- [j14]Prema Kumar Govindaswamy, Raviteja Kammari
, Vijaya Sankara Rao Pasupureddi
:
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. Int. J. Circuit Theory Appl. 51(8): 3637-3651 (2023) - [j13]Rakesh Varma Rena
, Raviteja Kammari
, Vijay Shankar Pasupureddi
:
0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 1065-1077 (2023) - [c28]Raviteja Kammari, Sarvesh Rajesh Tuckely, Vijay Shankar Pasupureddi:
A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS. APCCAS 2023: 16-20 - 2022
- [j12]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
:
A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects. Int. J. Circuit Theory Appl. 50(12): 4219-4233 (2022) - [c27]Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi:
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS 2022: 852-856 - [c26]Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi:
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS 2022: 857-861 - [c25]Rakesh Rena, Raviteja Kammari
, Vijaya Sankara Rao Pasupureddi:
Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture. MWSCAS 2022: 1-4 - 2021
- [j11]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
:
A 27-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. Circuits Syst. Signal Process. 40(11): 5553-5571 (2021) - [c24]Rakesh Rena, Suraj Kumar Verma
, Vijaya Sankara Rao Pasupureddi:
A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End. ISCAS 2021: 1-5 - 2020
- [j10]Raviteja Kammari
, Vijaya Sankara Rao Pasupureddi
:
Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS. Int. J. Circuit Theory Appl. 48(2): 198-213 (2020) - [j9]Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects. Microelectron. J. 104: 104899 (2020) - [c23]Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects. ISCAS 2020: 1-5 - [c22]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. ISVLSI 2020: 212-215
2010 – 2019
- 2019
- [j8]Ajinkya Kale
, Johannes Sturm
, Vijaya Sankara Rao Pasupureddi
:
A -40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization. Int. J. Circuit Theory Appl. 47(4): 549-560 (2019) - [j7]Ajinkya Kale
, Suchendranath Popuri, Michael Koeberle, Johannes Sturm
, Vijaya Sankara Rao Pasupureddi:
A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1166-1179 (2019) - [c21]Raviteja Kammari
, Vijaya Sankara Rao Pasupureddi
:
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. VDAT 2019: 202-214 - 2018
- [j6]Ajinkya Kale, Graciele Batistell, Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Wolfgang Bösch
, Johannes Sturm
:
Integration solutions for reconfigurable multi-standard wireless transceivers. Elektrotech. Informationstechnik 135(1): 18-23 (2018) - [c20]Ajinkya Kale, Johannes Sturm
, Vijaya Sankara Rao Pasupureddi:
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR. ISVLSI 2018: 316-320 - 2016
- [j5]Divya Duvvuri, Vijaya Sankara Rao Pasupureddi:
Design and analysis of a current mode integrated CTLE with charge mode adaptation. Microelectron. J. 53: 81-89 (2016) - [j4]Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology. IEEE Trans. Aerosp. Electron. Syst. 52(6): 2917-2929 (2016) - [c19]Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Johannes Sturm
:
A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers. ESSCIRC 2016: 185-188 - [c18]Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi:
A low power charge mode compressive acquisition of multichannel EEG signals. ISCAS 2016: 518-521 - [c17]Divya Duvvuri, Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi:
A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects. ISCAS 2016: 2342-2345 - [c16]Divya Duvvuri, Vijaya Sankara Rao Pasupureddi:
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation. ISVLSI 2016: 12-17 - [c15]Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate. VDAT 2016: 1-5 - 2015
- [c14]Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
MIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate. ISCAS 2015: 1842-1845 - [c13]Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate. ISQED 2015: 502-506 - 2014
- [c12]Divya Duvvuri, Vijaya Sankara Rao Pasupureddi, J. Chattopadhyay:
100-Mbps transceiver for enhanced MIL-STD-1553. APCCAS 2014: 316-319 - [c11]Ajinkya Kale, Vijaya Sankara Rao Pasupureddi, J. Chattopadhyay:
Design and simulation of a wideband channelized transceiver for DRFM applications. APCCAS 2014: 635-638 - [c10]Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi:
A 5-Gb/s adaptive CTLE with eye-monitoring for multi-drop bus applications. MWSCAS 2014: 410-413 - [c9]Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi:
A Low Power CMOS Imager Based on Distributed Compressed Sensing. VLSID 2014: 534-538 - [c8]R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti:
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. VLSID 2014: 575-579 - 2013
- [c7]Mahsa Shoaran
, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid
:
A low-power area-efficient compressive sensing approach for multi-channel neural recording. ISCAS 2013: 2191-2194 - [c6]Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi:
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy. VLSI Design 2013: 153-157 - 2012
- [j3]Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal:
A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination. Circuits Syst. Signal Process. 31(1): 31-49 (2012) - [j2]Vijaya Sankara Rao Pasupureddi, Pradip Mandal:
Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling. Int. J. Circuit Theory Appl. 40(4): 355-376 (2012) - 2011
- [j1]Vijaya Sankara Rao Pasupureddi, Pradip Mandal:
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect. Microelectron. J. 42(7): 957-965 (2011) - [c5]Mrigank Sharad, Vijaya Sankara Rao Pasupureddi, Pradip Mandal:
A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture. VLSI Design 2011: 12-17 - 2010
- [c4]Vijaya Sankara Rao Pasupureddi, Pradip Mandal:
Current-mode echo cancellation for full-duplex chip-to-chip data communication. APCCAS 2010: 748-751 - [c3]Vijaya Sankara Rao Pasupureddi, Pradip Mandal:
A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect. APCCAS 2010: 959-962
2000 – 2009
- 2009
- [c2]Vijaya Sankara Rao Pasupureddi, Pradip Mandal, Sunil Sachdev:
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect. ISVLSI 2009: 73-78 - 2008
- [c1]T. Venkata Kalyan
, Madhu Mutyam
, Vijaya Sankara Rao Pasupureddi:
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design 2008: 235-241
Coauthor Index
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