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ORCIDMichael P. Flynn
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- affiliation: University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
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Journal Articles
- 2024
[j66]Hsiang-Wen Chen
, Seungjong Lee, Michael P. Flynn:
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. IEEE J. Solid State Circuits 59(4): 1171-1183 (2024)- [j65]Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad Reza Haghighat, Michael P. Flynn:
A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer. IEEE J. Solid State Circuits 59(6): 1794-1808 (2024) - 2023
- [j64]Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. IEEE J. Solid State Circuits 58(4): 929-938 (2023) - [j63]Rundao Lu, Michael P. Flynn:
A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3821-3831 (2023) - 2022
- [j62]Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn:
An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. IEEE J. Solid State Circuits 57(6): 1812-1823 (2022) - [j61]Xinxin Wang, Reid Pinkham, Mohammed Affan Zidan, Fan-Hsuan Meng, Michael P. Flynn, Zhengya Zhang, Wei D. Lu:
TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 559-563 (2022) - 2021
- [j60]Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher Rozell, Justin Romberg, Michael P. Flynn:
A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. IEEE J. Solid State Circuits 56(3): 834-843 (2021) - [j59]Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn:
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver. IEEE J. Solid State Circuits 56(5): 1374-1386 (2021) - [j58]Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn:
Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver". IEEE J. Solid State Circuits 56(10): 3204 (2021) - [j57]Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn:
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. IEEE J. Solid State Circuits 56(12): 3681-3693 (2021) - 2020
- [j56]Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Michael P. Flynn:
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. IEEE J. Solid State Circuits 55(12): 3236-3247 (2020) - 2019
- [j55]Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn:
Design Considerations for Integrated Radar Chirp Synthesizers. IEEE Access 7: 13723-13736 (2019) - [j54]Sunmin Jang, Rundao Lu, Jaehun Jeong, Michael P. Flynn:
A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer. IEEE J. Solid State Circuits 54(5): 1304-1314 (2019) - [j53]Lu Jie, Boyi Zheng, Michael P. Flynn:
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 54(12): 3386-3395 (2019) - 2018
- [j52]Sunmin Jang, Jaehun Jeong, Rundao Lu, Michael P. Flynn:
A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS. IEEE J. Solid State Circuits 53(5): 1302-1312 (2018) - [j51]Mehmet Batuhan Dayanik, Michael P. Flynn:
Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System. IEEE J. Solid State Circuits 53(6): 1719-1730 (2018) - [j50]Shiming Song, Kyojin David Choo, Thomas Chen, Sunmin Jang, Michael P. Flynn, Zhengya Zhang:
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2269-2278 (2018) - [j49]Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn:
A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1589-1593 (2018) - 2017
- [j48]John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn:
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits 52(5): 1450-1457 (2017) - [j47]Yashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn:
A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2735-2745 (2017) - 2016
- [j46]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 51(3): 571 (2016) - [j45]Michael P. Flynn:
Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC. IEEE J. Solid State Circuits 51(3): 572 (2016) - [j44]Michael P. Flynn:
Introducing Short Regular Papers. IEEE J. Solid State Circuits 51(3): 573 (2016) - [j43]Hyungil Chae, Michael P. Flynn:
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. IEEE J. Solid State Circuits 51(3): 649-659 (2016) - [j42]Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Vivek Nagaraj, Theoden I. Netoff, Michael P. Flynn, Euisik Yoon:
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. IEEE J. Solid State Circuits 51(4): 955-965 (2016) - [j41]Michael P. Flynn, Pietro Andreani, SeongHwan Cho:
New Associate Editors. IEEE J. Solid State Circuits 51(5): 1063 (2016) - [j40]Jaehun Jeong, Nicholas Collins, Michael P. Flynn:
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators. IEEE J. Solid State Circuits 51(5): 1168-1176 (2016) - [j39]Michael P. Flynn:
Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 51(8): 1731 (2016) - 2015
- [j38]Michael P. Flynn:
New Associate Editors. IEEE J. Solid State Circuits 50(1): 3 (2015) - [j37]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(4): 811 (2015) - [j36]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(6): 1335 (2015) - [j35]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(7): 1511 (2015) - [j34]Yong Lim, Michael P. Flynn:
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. IEEE J. Solid State Circuits 50(10): 2331-2341 (2015) - [j33]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(11): 2471 (2015) - [j32]Yong Lim, Michael P. Flynn:
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC. IEEE J. Solid State Circuits 50(12): 2901-2911 (2015) - 2014
- [j31]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 49(1): 3 (2014) - [j30]Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. IEEE J. Solid State Circuits 49(2): 405-415 (2014) - [j29]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 49(3): 563 (2014) - [j28]Michael P. Flynn:
New Associate Editors. IEEE J. Solid State Circuits 49(7): 1459 (2014) - [j27]Michael P. Flynn:
New Associate Editor [Ken Suyama]. IEEE J. Solid State Circuits 49(10): 2087 (2014) - [j26]Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. IEEE J. Solid State Circuits 49(10): 2213-2227 (2014) - 2013
- [j25]Michael P. Flynn:
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 48(8): 1768 (2013) - [j24]Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 48(9): 1999 (2013) - 2012
- [j23]Praveen K. Yenduri, Aaron Z. Rocca, Aswin S. Rao, Shahrzad Naraghi, Michael P. Flynn, Anna C. Gilbert:
A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 502-515 (2012) - [j22]Jeffrey Fredenburg, Michael P. Flynn:
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 47(12): 2898-2904 (2012) - [j21]Jeffrey Fredenburg, Michael P. Flynn:
Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1396-1408 (2012) - [j20]David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn:
A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2846-2857 (2012) - 2011
- [j19]Chun C. Lee, Michael P. Flynn:
A SAR-Assisted Two-Stage Pipeline ADC. IEEE J. Solid State Circuits 46(4): 859-869 (2011) - [j18]Chun C. Lee, Michael P. Flynn:
A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1167-1177 (2011) - [j17]Jorge Pernillo, Michael P. Flynn:
A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 837-841 (2011) - 2010
- [j16]Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn:
A 9-bit, 14 μW and 0.06 mm 2 Pulse Position Modulation ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 45(9): 1870-1880 (2010) - [j15]Jongwoo Lee, Hyo-Gyuem Rhew, Daryl R. Kipke, Michael P. Flynn:
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. IEEE J. Solid State Circuits 45(9): 1935-1945 (2010) - 2009
- [j14]Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn:
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits 44(10): 2755-2765 (2009) - [j13]JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1807-1817 (2009) - 2008
- [j12]Mark A. Ferriss, Michael P. Flynn:
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. IEEE J. Solid State Circuits 43(11): 2464-2471 (2008) - 2007
- [j11]Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. IEEE J. Solid State Circuits 42(9): 1865-1872 (2007) - [j10]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. IEEE J. Solid State Circuits 42(9): 1976-1985 (2007) - 2006
- [j9]Fatih Kocer, Michael P. Flynn:
A new transponder architecture with on-chip ADC for long-range telemetry applications. IEEE J. Solid State Circuits 41(5): 1142-1148 (2006) - [j8]Sunghyun Park, Michael P. Flynn:
A regenerative comparator structure with integrated inductors. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(8): 1704-1711 (2006) - 2003
- [j7]Michael P. Flynn, Conor Donovan, L. Sattler:
Digital calibration incorporating redundancy of flash ADCs. IEEE Trans. Circuits Syst. II Express Briefs 50(5): 205-213 (2003) - 2002
- [j6]David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. IEEE J. Solid State Circuits 37(3): 310-316 (2002) - [j5]Conor Donovan, Michael P. Flynn:
A "digital" 6-bit ADC in 0.25-μm CMOS. IEEE J. Solid State Circuits 37(3): 432-437 (2002) - 2001
- [j4]David J. Foley, Michael P. Flynn:
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. IEEE J. Solid State Circuits 36(3): 417-423 (2001) - 1998
- [j3]Michael P. Flynn, Ben Sheahan:
A 400-Msample/s, 6-b CMOS folding and interpolating ADC. IEEE J. Solid State Circuits 33(12): 1932-1938 (1998) - 1996
- [j2]Michael P. Flynn, David J. Allstot:
CMOS folding A/D converters with current-mode interpolation. IEEE J. Solid State Circuits 31(9): 1248-1257 (1996) - 1992
- [j1]Michael P. Flynn, Sverre U. Lidholm:
A 1.2- mu m CMOS current-controlled oscillator. IEEE J. Solid State Circuits 27(7): 982-987 (1992)
Conference and Workshop Papers
- 2025
- [c58]Evangelos Dikopoulos, Ying-Tuan Hsu, Luke Wormald, Wei Tang, Zhengya Zhang, Michael P. Flynn:
25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time. ISSCC 2025: 1-3 - 2024
- [c57]Sungjin Oh, Hyunsoo Song, Jose Roberto Lopez Ruiz, Wangbo Chen, Sung-Yun Park, Michael P. Flynn, Euisik Yoon:
A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental sΔΔ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c56]Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn:
A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM). VLSI Technology and Circuits 2023: 1-2 - [c55]Seungheun Song, Taewook Kang, Seungjong Lee, Michael P. Flynn:
A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c54]Evelyn Ware, Justin M. Correll, Seungjong Lee, Michael P. Flynn:
6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration. ESSCIRC 2022: 325-328 - [c53]Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad R. Haghighat, Michael P. Flynn:
A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. ISSCC 2022: 500-502 - [c52]Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. VLSI Technology and Circuits 2022: 54-55 - [c51]Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn:
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits 2022: 264-265 - 2021
- [c50]Taewook Kang, Seungjong Lee, Mohammad Haghigat, Darren Abramson, Michael P. Flynn:
A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. CICC 2021: 1-2 - [c49]Boyi Zheng, Lu Jie, Michael P. Flynn:
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. ESSCIRC 2021: 511-514 - [c48]Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn:
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. ISSCC 2021: 167-169 - [c47]Rundao Lu, Michael P. Flynn:
A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c46]Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher J. Rozell, Justin Romberg, Michael P. Flynn:
A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS. CICC 2020: 1-4 - [c45]Michael P. Flynn, Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell:
Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited). CICC 2020: 1-8 - [c44]Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn:
9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. ISSCC 2020: 160-162 - [c43]Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn:
An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. VLSI Circuits 2020: 1-2 - 2019
- [c42]John Bell, Michael P. Flynn:
A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS. ESSCIRC 2019: 1-4 - [c41]Lu Jie, Boyi Zheng, Michael P. Flynn:
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC. ISSCC 2019: 332-334 - 2018
- [c40]Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn:
A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. ISSCC 2018: 250-252 - [c39]Adam E. Mendrela, Sung-Yun Park, Mihály Vöröslakos, Michael P. Flynn, Euisik Yoon:
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. VLSI Circuits 2018: 125-126 - 2016
- [c38]Kyojin David Choo, John Bell, Michael P. Flynn:
27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. ISSCC 2016: 460-461 - [c37]Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn:
A 16-channel noise-shaping machine learning analog-digital interface. VLSI Circuits 2016: 1-2 - 2015
- [c36]Jeffrey Fredenburg, Michael P. Flynn:
ADC trends and impact on SAR ADC architecture and analysis. CICC 2015: 1-8 - [c35]Mehmet Batuhan Dayanik, Nicholas Collins, Michael P. Flynn:
A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution. ESSCIRC 2015: 376-379 - [c34]Yong Lim, Michael P. Flynn:
26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC. ISSCC 2015: 1-3 - [c33]Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Cynthia A. Chestek, Michael P. Flynn, Euisik Yoon:
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression. VLSIC 2015: 108- - 2014
- [c32]Yong Lim, Michael P. Flynn:
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. ISSCC 2014: 202-203 - [c31]Chunyang Zhai, Jeffrey Fredenburg, John Bell, Michael P. Flynn:
An N-path filter enhanced low phase noise ring VCO. VLSIC 2014: 1-2 - 2013
- [c30]Jorge Pernillo, Michael P. Flynn:
A 9b 2GS/s 45mW 2X-interleaved ADC. ESSCIRC 2013: 125-128 - [c29]Michael P. Flynn, John Khoury:
EP2: You're hired! The top 25 interview questions for circuit designers. ISSCC 2013: 516 - 2012
- [c28]Hyo-Gyuem Rhew, Michael P. Flynn, JunYoung Park:
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. ESSCIRC 2012: 233-236 - [c27]Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. ISSCC 2012: 148-150 - [c26]Jeffrey Fredenburg, Michael P. Flynn:
A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. ISSCC 2012: 468-470 - [c25]Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. VLSIC 2012: 70-71 - 2011
- [c24]Praveen K. Yenduri, Anna C. Gilbert, Michael P. Flynn, Shahrzad Naraghi:
Rand PPM: A lowpower compressive sampling analog to digital converter. ICASSP 2011: 5980-5983 - 2010
- [c23]David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn:
A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC. CICC 2010: 1-4 - [c22]Andres Tamez, Jeffrey A. Fredenburg, Michael P. Flynn:
An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS. ESSCIRC 2010: 238-241 - 2009
- [c21]Mark A. Ferriss, David T. Lin, Michael P. Flynn:
A fractional-N PLL modulator with flexible direct digital phase modulation. CICC 2009: 49-52 - [c20]Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn:
A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS. ISSCC 2009: 168-169 - 2008
- [c19]JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. CICC 2008: 347-350 - [c18]Joshua Jaeyoung Kang, David T. Lin, Li Li, Michael P. Flynn:
A reconfigurable FIR filter embedded in a 9b successive approximation ADC. CICC 2008: 711-714 - 2007
- [c17]Ivan Bogue, Michael P. Flynn:
A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. CICC 2007: 337-340 - [c16]Mark A. Ferriss, Michael P. Flynn:
A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. ISSCC 2007: 352-608 - 2006
- [c15]Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn:
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. CICC 2006: 489-492 - [c14]JunYoung Park, Michael P. Flynn:
A Low Jitter Multi-Phase PLL with Capacitive Coupling. CICC 2006: 753-756 - [c13]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. ISSCC 2006: 1490-1499 - [c12]Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4GS/s 4b Flash ADC in 0.18µm CMOS. ISSCC 2006: 2330-2339 - 2005
- [c11]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. CICC 2005: 361-364 - [c10]Sunghyun Park, Michael P. Flynn:
Design techniques for high performance CMOS flash analog-to-digital converters. ECCTD 2005: 131-134 - [c9]Fatih Kocer, Michael P. Flynn:
A new transponder architecture for long-range telemetry applications. ECCTD 2005: 177-180 - [c8]Michael P. Flynn, Joshua Jaeyoung Kang:
Global signaling over lossy transmission lines. ICCAD 2005: 985-992 - [c7]JunYoung Park, Michael P. Flynn:
Capacitively averaged multi-phase LC oscillators. ISCAS (3) 2005: 2651-2654 - 2004
- [c6]Fatih Kocer, Paul M. Walsh, Michael P. Flynn:
An RF powered, wireless temperature sensor in quarter micron CMOS. ISCAS (4) 2004: 876-879 - 2001
- [c5]David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS. CICC 2001: 123-126 - [c4]Conor Donovan, Michael P. Flynn:
A 'digital' 6-bit ADC in 0.25 μm CMOS. CICC 2001: 145-148 - 2000
- [c3]David J. Foley, Michael P. Flynn:
CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator. CICC 2000: 371-374 - [c2]David J. Foley, Michael P. Flynn:
A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS. ISCAS 2000: 249-252 - 1999
- [c1]Michael P. Flynn, Michael Twohig, Raymond Byrne, Hooman Reyhani, John Ryan:
A BiCMOS preamplifier/write-driver IC for tape drive. CICC 1999: 329-332
Coauthor Index
Jeffrey Fredenburg
aka: Jeffrey A. Fredenburg
aka: Jeffrey A. Fredenburg
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Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-06-17 00:23 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
