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ORCIDECCTD 2005: Cork, Ireland
- Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005. IEEE 2005, ISBN 0-7803-9066-0
Volume 1
- Giovanni De Micheli:
Plenary lecture [Second page is blank]. 1-2 - Kuniyasu Shimizu, Tetsuro Endo:
Stability of the quasi-periodic and periodic attractors constrained to the hyper-plane in a ring of three-coupled hard-type oscillators. 3-6 - Takuji Kousaka, Yue Ma:
Bifurcation analysis in a hybrid time delay system. 7-10 - Tomoumi Yagasaki, Yoshihiko Horio, Kazuyuki Aihara:
One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. 11-14 - Markku Åberg, Jan Saijets:
DC and AC characteristics and modeling of Si SSD-nano devices. 15-18 - Sebastian Prot, Mark F. Flanagan
, Conor Heneghan:
Conditional quasi maximum-likelihood receiver for clipped OFDM signals. 19-22 - Luís Nero Alves, Rui L. Aguiar:
On the usage of delayed-feedback in amplifiers. 23-26 - Raimondo Luzzi, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti:
2-V CMOS current operational amplifier with high CMRR. 27-30 - Nobukazu Takai, Shinji Nomura:
Rail-to-rail OTA utilizing linear V-I conversion circuit using single channel MOSFETs for input stage. 31-34 - Belén Calvo, Santiago Celma, Pedro A. Martínez, Maria Teresa Sanz:
1.8 V.0.35 μm CMOS wideband programmable gain amplifier. 35-38 - Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs:
Analysis of coil parameter extraction methods for on-chip inductor design. 39-42 - Jacek Izydorczyk:
Simulation of ferrites by SPICE. 43-46 - Timo Veijola:
Compact model for a cantilever beam MEM contact switch. 47-50 - Caroline Lelandais-Perrault, Daniel Poulton, Jacques Oksman:
Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolution. 51-54 - K. Ola Andersson, Mark Vesterbacka:
A yield-enhancement strategy for binary-weighted DACs. 55-58 - Jeffrey O. Coleman:
Modeling finite-memory nonlinearity in unit DAC elements, binary storage channels, and BPSK data channels. 59-62 - Chatree Budsabathon, Akinori Nishihara:
Dithered subband coding with spectral subtraction. 63-66 - Mark F. Flanagan, Anthony D. Fagan:
A Gradient-based adaptive algorithm for minimum phase-all pass decomposition of an FIR system. 67-70 - Naomi Harte, Niall P. Hurley, Conor Fearon, Scott Rickard:
Towards a hardware realization of time-frequency source separation of speech. 71-74 - Fausto Sargeni, Vincenzo Bonaiuto, Maurizio Bonifazi:
Time division digital programmable OTA for cellular neural networks. 75-78 - Péter Sonkoly, Sándor Kocsárdi, Péter Kozma, Péter Szolgay:
Inverse elastic wave propagation modeling on CNN-UM architecture. 79-82 - Mario Salerno, Daniele Casali, Giovanni Costantini, Massimo Carota:
A customizable tool for cellular nonlinear network simulation. 83-86 - Shadi Tawfik, Tian Tong, Troels Studsgaard Nielsen, Torben Larsen:
A 1.9 GHz CMOS class E power amplifier with +29 dBm output power and 58% PAE. 87-90 - Shashikanth Bobba, Ashoka S. V., Thomas Mattsson, Stefan Nilsson:
Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologies. 91-94 - Ali Fard, Denny Åberg:
A reconfigurable CMOS VCO with an automatic amplitude controller for multi-band RF front-ends. 95-98 - Mikko Loikkanen, Juha Kostamovaara:
Improving capacitive drive capability of two-stage op amps with current buffer. 99-102 - Emanuele Bottino, Maurizio Valle:
Integrated low noise preamplifier for biologic-electronics interfaces. 103-106 - Andrzej Handkiewicz, Radoslaw Rudnicki, Marek Kropidlowski:
Switched current filter design with the use of integrators composed of equal size transistors. 107-110 - William Prodanov, Maurizio Valle:
A behavioral model for the nonlinear on-resistance in sample-and-hold analog switches. 111-114 - M. Helena Fino:
A simple submicron MOSFET model and its application to the analytical characterization of analog circuits. 115-118 - Juan Pablo Alegre, Santiago Celma, Maria Teresa Sanz, Belén Calvo:
Comparative study of MOST resistive configurations. 119-122 - Yujin Park, Sanghoon Hwang, Minkyu Song:
An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique. 123-126 - Erik Säll, Mark Vesterbacka:
6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. 127-130 - Sunghyun Park, Michael P. Flynn:
Design techniques for high performance CMOS flash analog-to-digital converters. 131-134 - Joachim F. Selinger, Axel Wenzler:
Robust reconstruction of nonuniformly sampled signals. 135-138 - Lars Wanhammar, Kenny Johansson, Oscar Gustafsson:
Efficient sine and cosine computation using a weighted sum of bit-products. 139-142 - Fredrik Edman, Viktor Öwall:
Fixed-point implementation of a robust complex valued divider architecture. 143-146 - Ivo Bolsens:
Plenary lecture [Second page is blank]. 147-148 - Víctor M. Brea, Mika Laiho, Ari Paasio:
Robustness improvement in binary cellular non-linear network architectures. 149-152 - Xavier Vilasís-Cardona, Mireia Vinyoles-Serra:
On cellular neural network learning. 153-156 - Ahmed Ayoub, Szabolcs Tõkés:
A new CNN template for POAC peak enhancement. 157-160 - Lasse Aaltonen, Mikko Saukoski, Kari Halonen:
Design of clock generating fully integrated PLL using low frequency reference signal. 161-164 - Luca Antonio De Michele, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti:
Chaos-based high-EMC spread-spectrum clock generator. 165-168 - Andreas Mögel, Jörg Krupar, Wolfgang M. Schwarz:
EMI performance of spread spectrum clock signals with respect to the IF bandwidth of the EMC standard. 169-172 - Joe C. P. Liu, Chi K. Tse, Franki N. K. Poon, M. H. Pong, William Y. M. Lai:
General impedance synthesizer using minimal configuration of switching converters. 173-176 - Octavian Dranga, Chi K. Tse, Siu Chung Wong:
Stability analysis of complete two-stage power-factor-correction power supplies. 177-180 - Serhan Yamaçli, Sadri Özcan, Hakan Kuntman:
Resistorless KHN biquad using an DDA (difference diffference amplifier) and two CCCIIs (controlled current conveyor). 181-184 - Marko Neitola, Timo Rahkonen:
A fully automated flowgraph analysis tool for Matlab. 185-188 - Masaya Yoshikawa, Hidekazu Terai:
Hybrid genetic algorithm engine for high-speed floorplanning. 189-192 - K. L. Man:
SystemCFL: a formalism for hardware/software codesign. 193-196 - Juan M. Carrillo, Miguel A. Montecelo, Harald Neubauer, Hans Hauer, J. Francisco Duque-Carrillo:
1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technology. 197-200 - Esmaeil Najafi Aghdam, Philippe Bénabès:
Higher order dynamic element matching by shortened tree-structure in delta-sigma modulators. 201-204 - Cristina Della Fiore, Franco Maloberti:
Design of ΣΔ modulators with reduced number of operational amplifiers. 205-208 - François-Xavier Coudoux, Marc Gazalet, Patrick Corlay:
A DCT-domain postprocessor for color bleeding removal. 209-212 - Mattias O'Nils, Per-Robert Lilljefjäll, Benny Thörnberg:
Data partitioning for parallel implementation of real-time video processing systems. 213-216 - Adam Luczak, Pawel Garstecki:
A flexible architecture for image reconstruction in H.264/AVC decoders. 217-220 - Barry O'Donnell, Paul F. Curran, Orla Feely:
On the bifurcation properties of a class of differentiable mappings. 221-224 - Zhong Zhang, Guanrong Chen:
Chaotic motion generation with applications to liquid mixing. 225-228 - Yoko Uwate, Yoshifumi Nishio:
Modeling using 1-D map of complex behavior in coupled chaotic circuits with intermittency. 229-232 - Emer Condon, Paul F. Curran, Ketan Mistry, Orla Feely:
On the steady state behaviour of an nth-order class of nonlinear mappings. 233-236 - Mikko Hotti, Jussi Ryynänen, Kari Halonen:
RC-load analysis of the downconversion mixer IIP2. 237-240 - Morgan Fitzgibbon, Diarmuid McSwiney, Dermot O'Keeffe, Jyoti Mondal, David Redmond, William Waldie:
A single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) class 12 applications. 241-244 - Aránzazu Otín, Concepción Aldea, Santiago Celma:
Low voltage LC-ladder Gm-C low-pass filters with 42-215 MHz tunable range. 245-248 - Calogero D. Presti, Francesco Carrara, Giuseppe Palmisano:
Variable-gain up-conversion mixer with current reuse for 5-GHz W-LAN applications. 249-252 - Mikko Varonen, Mikko Kärkkäinen, Pekka Kangaslahti, Kari Halonen:
Metamorphic HEMT amplifier for K- and Ka-band applications. 253-256 - Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti:
Switched-capacitor body-biasing technique for very low voltage CMOS amplifiers. 257-260 - Juan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo:
1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth product. 261-264 - Giuseppe Di Cataldo, Salvatore Pennisi:
CMOS interface for differential capacitive transducers. 265-268 - Hold Omid Rajaee, Mehrdad Sharif Bakhtiar:
A low voltage, high speed current mode sample and hold for high precision applications. 269-272 - Alfio Dario Grasso, Salvatore Pennisi:
Current-steering D/A converter based on triple tail cell. 273-276 - Francis C. M. Lau, Alan Daly, William P. Marnane:
Optimised Montgomery domain inversion on FPGA. 277-280 - Juan Carlos López-García, Marco A. Moreno-Armendáriz, Jordi Riera-Babures, Marco Balsi, Xavier Vilasís-Cardona:
Real time vision by FPGA implemented CNNs. 281-284 - D. Bianchi, Gian Carlo Cardarilli, Andrea Del Re, A. Malatesta, Marco Re:
FPGA implementation of a general purpose HMM processor based on token passing algorithm. 285-288 - Christian Spagnol, William P. Marnane, Emanuel M. Popovici:
Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder. 289-292 - Martin Vogels, Georges G. E. Gielen:
Systematic top-down design of A/D converters. 293-296 - Alessandro Cabrini, Franco Maloberti:
Use of non-linear Chua's circuit for on-line offset calibration of ADC. 297-300 - Stephen O'Driscoll, Teresa H. Meng:
Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell. 301-304 - Marko Kosunen, Kari Halonen:
Sampling jitter and power supply interference in current-steering D/A converters. 305-308 - Carsten Wegener, Michael Peter Kennedy:
Innovation to overcome limitations of test equipment. 309-314 - Iulian B. Ciocoiu:
Occluded face recognition using parts-based representation methods. 315-318 - Takenobu Matsuura, Kazuki Izumi:
A realization of FIR system for on-line writer recognition. 319-322 - Shuitsu Matsumura, Tsuyoshi Takebe:
An effective compression scheme for prediction errors on lossless image coding. 323-326 - Sarunas Paulikas, Dalius Navakauskas:
Recognition of isolated words corrupted by impulsive noise. 327-330 - Peter Michael Goebel, Ahmed Nabil Belbachir, Michael Truppe:
Background removal in dental panoramic X-ray images by the A-Trous multiresolution transform. 331-334
Volume 2
- Árpád I. Csurgay, Wolfgang Porod, Stephen M. Goodnick:
The circuit paradigm in nanoelectronics - field-coupled and hybrid nanoelectronic circuits. 1-6 - Alon Ascoli, Paul F. Curran, Orla Feely:
A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit. 7-10 - Pedro Ramírez, Andrés Guesalaga:
Non-linear dynamics in servo positioning loops. 11-14 - Seiichiro Moro, Tadashi Matsumoro:
On phase pattern transition in star-coupled Wien-bridge oscillators with parameter deviations. 15-18 - Erik Lindberg:
Oscillators and operational amplifiers. 19-22 - Ali Banai, Forouhar Farzaneh:
Theoretical investigation of the stability of the modes in an array of coupled oscillators for linear and circular arrangements. 23-26 - John Vosper, Richard Deloughry, Brett Wilson:
Multiphase active-RC sinusoidal oscillators incorporating lowpass and allpass sections. 27-30 - Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa:
A design scheme for sampling switch in active matrix LCD. 31-34 - Alessandro Cabrini, Laura Gobbi, Guido Torelli:
A theoretical discussion on performance limits of CMOS charge pumps. 35-38 - Paolo Stefano Crovetti, Franco L. Fiori:
Nonlinear effects of RF interference in SC circuits. 39-42 - Angelo Brambilla, Giancarlo Storti Gajani, Amedeo Premoli:
Partitioning large circuits to speed up numerical simulations. 43-46 - Pedro C. Ventura, Marco Oliveira:
A methodology for fast reuse of analog circuit schematics. 47-50 - Andreas Bauer:
Efficient algorithms for the computation and application of Volterra kernels in the behavior analysis of nonlinear circuits and systems. 51-54 - Olujide A. Adeniran, Andreas Demosthenous:
Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs. 55-58 - José L. Ausín, Guido Torelli, J. Francisco Duque-Carrillo:
Linearity enhancement of oversampled pipeline A/D converters using sigma-delta modulation. 59-62 - Takeshi Koike, Akira Hyogo, Keitaro Sekine:
A 2.0-V folding circuit using current limiting amplifier for ADC. 63-66 - Marco Balsi, Giuseppe Filosa, Giancarlo Valente, Patrizia Pantano:
Constrained ICA for functional magnetic resonance imaging. 67-70 - Ichiro Matsuda, Taichiro Shiodera, Hiroki Maeda, Susumu Itoh:
Lossless video coding using bi-directional 3D prediction optimized for each frame. 71-74 - Krzysztof Slot, Hubert Nowak:
Feature space derivation for isolated utterance reading with discriminant deformable models. 75-78 - Géza Kolumbán:
UWB technology: chaotic communications versus noncoherent impulse radio. 79-82 - Keith O'Donoghue, Michael Peter Kennedy, Peadar Forbes:
A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diode. 83-86 - Piotr Dudek, V. D. Juncu:
An area and power efficient discrete-time chaos generator circuit. 87-90 - Behnam Sedighi, Hold Omid Rajaee, Amin Jahanian, Mehrdad Sharif Bakhtiar:
A 1.5V 150MS/s current-mode sample-and-hold circuit. 91-94 - Behnam Sedighi, Mehrdad Sharif Bakhtiar:
A 1.5V 60MS/s sampled-data filter in 0.18μm CMOS. 95-98 - Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
A high-speed sense-amplifier based flip-flop. 99-102 - Antonio J. López-Martín, Jaime Ramírez-Angulo, Ramón González Carvajal:
Design of high-performance tunable filters based on current conveyors. 103-106 - Karel Hajek, Jirí Sedlácek, Bohumir Sviezeny:
Minimization of offset of the tunable LP filters. 107-110 - Klaus Schmalz, Mykhaylo A. Teplechuk, John I. Sewell:
A class AB 6th order log-domain filter in BiCMOS with 100-500 MHz tuning range. 111-114 - David G. Haigh:
Systematic synthesis of operational amplifier circuits by admittance matrix expansion. 115-118 - Engin Deniz, Günhan Dündar:
Performance estimator for an analog design automation system using EKV-modeled analog circuits. 119-122 - Mattias O'Nils, Bengt Oelmann, Kent Bertilsson, Hans-Erik Nilsson, Göran Thungström:
A project based master's programme for SoF/SoC based sensor systems. 123-126 - Jaap Hoekstra:
Prediction of Coulomb blockade in arbitrary environments. 127-130 - Nicholas P. Carter, Steve Ferrera, Love Kothari, Stanley Ye:
Hall-effect circuits and architectures for non-volatile system design. 131-134 - Woo Hyung Lee, Pinaki Mazumder:
New logic circuits consisting of quantum dots and CMOS. 135-138 - Yuri Dolgin, Ezra Zeheb:
Computing minimum-phase factors of polynomials. 139-142 - D. Adamidis, Haridimos T. Vergos:
Modulo 2n - 1 multiplication/sum-of-squares units. 143-146 - Corneliu Rusu, Jaakko Astola:
Argument principle and discrete Fourier transform. 147-150