"A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer ..."

David J. Foley, Michael P. Flynn (2000)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2000.856308

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/FoleyF00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/FoleyF00
David J. Foley, Michael P. Flynn:
A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS. ISCAS 2000: 249-252

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.