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2020 – today
- 2024
[j75]Flavia Guella
, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina:
MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2105-2118 (2024)- [c94]Michele Caon, Vincenzo Petrolo, Mattia Mirigaldi, Flavia Guella, Guido Masera, Maurizio Martina:
Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling. CF (Companion) 2024 - [c93]Alessandra Dolmeta, Emanuele Valpreda, Maurizio Martina, Guido Masera:
Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber. CF (Companion) 2024 - [i21]Eugenio Ressa, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique:
TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. CoRR abs/2402.09780 (2024) - [i20]Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza:
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR abs/2406.14263 (2024) - 2023
- [j74]Kristjane Koleci, Paolo Mazzetti, Maurizio Martina, Guido Masera:
A Flexible NTT-Based Multiplier for Post-Quantum Cryptography. IEEE Access 11: 3338-3351 (2023) - [j73]Alessandra Dolmeta, Maurizio Martina, Guido Masera:
Comparative Study of Keccak SHA-3 Implementations. Cryptogr. 7(4): 60 (2023) - [j72]Simone Favero, Maurizio Martina, Guido Masera:
Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 131-135 (2023) - [c92]Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera:
LOKI Low-Latency Open-Source Kyber-Accelerator IPs. ApplePies 2023: 29-35 - [c91]Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina:
TEMET: Truncated REconfigurable Multiplier with Error Tuning. ApplePies 2023: 370-377 - [c90]Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera:
Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber. CF 2023: 381-382 - [c89]Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique:
SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. IJCNN 2023: 1-9 - [c88]Alessandra Dolmeta, Maurizio Martina, Guido Masera:
Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives. PRIME 2023: 209-212 - [c87]Emanuele Valpreda, Giuseppe Palumbo, Michele Caon, Guido Masera, Maurizio Martina:
ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information. PRIME 2023: 277-280 - [c86]William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa:
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS 2023: 363-378 - [i19]Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique:
SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. CoRR abs/2304.03986 (2023) - [i18]Fabrizio Ottati, Giovanna Turvani, Marco Vacca, Guido Masera:
Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories. CoRR abs/2304.04995 (2023) - 2022
- [c85]Kristjane Koleci, Lorenzo Cecchetti, Guido Masera, Maurizio Martina, Massimo Ruo Roch:
A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography. ApplePies 2022: 90-96 - [c84]Giuseppe Aiello, Beatrice Bussolino, Emanuele Valpreda, Massimo Ruo Roch, Guido Masera, Maurizio Martina, Stefano Marsi:
NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. ICIP 2022: 926-930 - [c83]Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique:
CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. IJCNN 2022: 1-8 - [c82]Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique:
LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. IROS 2022: 79-86 - [c81]Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique:
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. ISLPED 2022: 27:1-27:6 - [i17]Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique:
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. CoRR abs/2206.10200 (2022) - [i16]Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique:
CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. CoRR abs/2208.00331 (2022) - [i15]Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique:
LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. CoRR abs/2208.02253 (2022) - 2021
- [j71]Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina, Guido Masera:
Efficient Hardware Implementation of the LEDAcrypt Decoder. IEEE Access 9: 66223-66240 (2021) - [j70]Walid Walid, Muhammad Awais, Ashfaq Ahmed, Guido Masera, Maurizio Martina:
Real-time implementation of fast discriminative scale space tracking algorithm. J. Real Time Image Process. 18(6): 2347-2360 (2021) - [c80]Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique:
DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. IJCNN 2021: 1-9 - [c79]Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique:
CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. IJCNN 2021: 1-10 - [c78]Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique:
R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. IROS 2021: 6315-6321 - [i14]Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique:
CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. CoRR abs/2107.00401 (2021) - [i13]Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique:
DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. CoRR abs/2107.00415 (2021) - [i12]Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique:
R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. CoRR abs/2109.00533 (2021) - 2020
- [j69]Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique:
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. IEEE Access 8: 225134-225180 (2020) - [j68]Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Muhammad Shafique, Guido Masera, Maurizio Martina:
An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. Future Internet 12(7): 113 (2020) - [j67]Riccardo Peloso, Maurizio Capra, Luigi Sole, Massimo Ruo Roch, Guido Masera, Maurizio Martina:
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. Sensors 20(5): 1405 (2020) - [j66]Jurgen Kello, Massimo Ruo Roch, Guido Masera, Maurizio Martina:
Low-Complexity Reconfigurable DCT-V Architecture. IEEE Trans. Circuits Syst. 67-II(12): 3417-3421 (2020) - [j65]Maurizio Masera, Guido Masera, Maurizio Martina:
An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding. IEEE Trans. Circuits Syst. Video Technol. 30(1): 232-242 (2020) - [c77]Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Vojtech Mrazek, Maurizio Martina, Guido Masera, Muhammad Shafique:
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS 2020: 34-36 - [c76]Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique:
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. DAC 2020: 1-6 - [c75]Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique:
FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. IJCNN 2020: 1-8 - [c74]Kristjane Koleci, Marco Baldi, Maurizio Martina, Guido Masera:
A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography. ITASEC 2020: 141-152 - [i11]Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique:
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. CoRR abs/2004.07116 (2020) - [i10]Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique:
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. CoRR abs/2012.11233 (2020)
2010 – 2019
- 2019
- [j64]Maurizio Capra, Riccardo Peloso, Guido Masera, Massimo Ruo Roch, Maurizio Martina:
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. Future Internet 11(4): 100 (2019) - [j63]Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera:
LDPC check node implementation using reversible logic. IET Circuits Devices Syst. 13(4): 443-455 (2019) - [j62]Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina:
On the Effect of Approximate-Computing in Motion Estimation. J. Low Power Electron. 15(1): 40-50 (2019) - [c73]Luigi Sole, Riccardo Peloso, Maurizio Capra, Massimo Ruo Roch, Guido Masera, Maurizio Martina:
VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT). ApplePies 2019: 137-143 - [i9]Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique:
X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations. CoRR abs/1905.10142 (2019) - 2018
- [j61]Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross:
A Multi-Kernel Multi-Code Polar Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4413-4422 (2018) - [c72]Paolo Selvo, Maurizio Masera, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina:
An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. ApplePies 2018: 245-251 - [c71]Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina:
Approximate-Computing Architectures for Motion Estimation in HEVC. NGCAS 2018: 190-193 - [c70]Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross:
Efficient Operation Scheduling in Successive-Cancellation-based polar decoders. SiPS 2018: 83-87 - [i8]Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross:
A Multi-Kernel Multi-Code Polar Decoder Architecture. CoRR abs/1802.00580 (2018) - 2017
- [j60]Maurizio Masera, Lorenzo Re Fiorentin, Enrico Masala, Guido Masera, Maurizio Martina:
Analysis of HEVC transform throughput requirements for hardware implementations. Signal Process. Image Commun. 57: 173-182 (2017) - [j59]Maurizio Masera, Maurizio Martina, Guido Masera:
Adaptive Approximated DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 27(12): 2714-2725 (2017) - [c69]Simone Aiassa, Paolo Motto Ros, Guido Masera, Maurizio Martina:
A low power architecture for AER event-processing microcontroller. BioCAS 2017: 1-4 - [c68]Erik Anzalone, Maurizio Capra, Riccardo Peloso, Maurizio Martina, Guido Masera:
Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network. IIH-MSP (1) 2017: 79-89 - [c67]Giovanni Renda, Maurizio Masera, Maurizio Martina, Guido Masera:
Approximate Arai DCT Architecture for HEVC. NGCAS 2017: 133-136 - [c66]Maurizio Masera, Maurizio Martina, Guido Masera:
Odd type DCT/DST for video coding: Relationships and low-complexity implementations. SiPS 2017: 1-6 - 2016
- [j58]Syed Azhar Ali Zaidi, Abuduwaili Tuoheti, Maurizio Martina, Guido Masera:
FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories. IEEE Des. Test 33(6): 77-84 (2016) - [j57]Lorenzo Guerrieri, Guido Masera, Igor S. Stievano, Paola Bisaglia, Williams Richard Garcia Valverde, Mara Concolato:
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator. IEEE Trans. Ind. Electron. 63(5): 3081-3090 (2016) - [c65]Waqar Ahmad, Javed Iqbal, Maurizio Martina, Guido Masera:
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters. EMS 2016: 79-82 - [c64]Lorenzo Re Fiorentin, Maurizio Masera, Sabino Mantovano, Paola Sunna, Guido Masera, Maurizio Martina:
Comparison between HEVC and Thor based on objective and subjective assessments. IWSSIP 2016: 1-4 - 2015
- [j56]Carlo Condo, Amer Baghdadi, Guido Masera:
Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. 34(5): 1571-1593 (2015) - [j55]Stylianos Papaharalabos, P. Takis Mathiopoulos, Maurizio Martina, Guido Masera:
Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations". IEEE Commun. Lett. 19(11): 2049-2050 (2015) - [j54]Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera:
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. Integr. 50: 139-146 (2015) - [j53]Carlo Condo, Guido Masera, Paolo Montuschi:
Unequal Error Protection of Memories in LDPC Decoders. IEEE Trans. Computers 64(10): 2981-2993 (2015) - [j52]Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini:
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2103-2113 (2015) - [j51]Muhammad Usman Shahid, Ashfaq Ahmed, Maurizio Martina, Guido Masera, Enrico Magli:
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware. IEEE Trans. Circuits Syst. Video Technol. 25(4): 701-715 (2015) - [c63]Maurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala:
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. DASIP 2015: 1-6 - [c62]Masoud Shahshahani Amirhossein, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi, Guido Masera:
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. DATE 2015: 1479-1484 - [c61]Waqar Ahmad, Maurizio Martina, Guido Masera:
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding. IC3D 2015: 1-8 - 2014
- [j50]Maurizio Martina, Carlo Condo, Guido Masera, Maurizio Zamboni:
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. IEEE Embed. Syst. Lett. 6(4): 77-80 (2014) - [j49]Carlo Condo, Amer Baghdadi, Guido Masera:
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. 8(12): 2171-2180 (2014) - [j48]Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera:
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. 21(11): 1380-1384 (2014) - [j47]Carlo Condo, Guido Masera:
Unified turbo/LDPC code decoder architecture for deep-space communications. IEEE Trans. Aerosp. Electron. Syst. 50(4): 3115-3125 (2014) - [j46]Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini:
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 890-894 (2014) - [j45]Maurizio Martina, Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera:
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures. IEEE Trans. Instrum. Meas. 63(3): 531-537 (2014) - [j44]Maurizio Awais, Guido Masera, Maurizio Martina, Guido Montorsi:
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation. IEEE Trans. Signal Process. 62(15): 3965-3975 (2014) - [c60]Simone Zezza, Guido Masera, Saeid Nooshabadi:
A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic. ISCAS 2014: 902-905 - [c59]Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini:
Molecular transistor circuits: From device model to circuit simulation. NANOARCH 2014: 129-134 - [c58]Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera:
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications. PDP 2014: 418-423 - 2013
- [j43]Bin Wu, Guido Masera:
Analysis on parallel implementations of fixed-complexity sphere decoder. Sci. China Inf. Sci. 56(4): 1-11 (2013) - [j42]Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca:
Power Control for Crossbar-Based Input-Queued Switches. IEEE Trans. Computers 62(1): 74-82 (2013) - [j41]Simone Zezza, Saeid Nooshabadi, Guido Masera:
A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 951-964 (2013) - [j40]Carlo Condo, Maurizio Martina, Guido Masera:
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1441-1454 (2013) - [j39]Maurizio Martina, Guido Masera:
Improving Network-on-Chip-based Turbo Decoder Architectures. J. Signal Process. Syst. 73(1): 83-100 (2013) - [c57]Syed Azhar Ali Zaidi, Muhammad Awais, Carlo Condo, Maurizio Martina, Guido Masera:
FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories. DASIP 2013: 190-195 - [c56]Carlo Condo, Amer Baghdadi, Guido Masera:
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD 2013: 168-174 - [c55]Ashfaq Ahmed, Muhammad Usman Shahid, Maurizio Martina, Enrico Magli, Guido Masera:
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. DSD 2013: 288-292 - 2012
- [j38]Stylianos Papaharalabos, Panayiotis Takis Mathiopoulos, Guido Masera, Maurizio Martina:
Non-recursive max* operator with reduced implementation complexity for turbo decoding. IET Commun. 6(7): 702-707 (2012) - [j37]Bin Wu, Guido Masera:
Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder. IET Commun. 6(9): 1111-1118 (2012) - [j36]M. Tamagnone, Maurizio Martina, Guido Masera:
An application specific instruction set processor based implementation for signal detection in multiple antenna systems. Microprocess. Microsystems 36(3): 245-256 (2012) - [j35]Andrea Dario Giancarlo Biroli, Maurizio Martina, Guido Masera:
An LDPC Decoder Architecture for Wireless Sensor Network Applications. Sensors 12(2): 1529-1543 (2012) - [j34]Maurizio Martina, Guido Masera, Stylianos Papaharalabos, P. Takis Mathiopoulos, Fotios Gioulekas:
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders. IEEE Trans. Instrum. Meas. 61(4): 888-895 (2012) - [j33]Luca Gaetano Amarù, Maurizio Martina, Guido Masera:
High Speed Architectures for Finding the First two Maximum/Minimum Values. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2342-2346 (2012) - [j32]Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy:
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012: 549768:1-549768:2 (2012) - [j31]Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera:
A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. VLSI Design 2012: 826350:1-826350:14 (2012) - [c54]Carlo Condo, Maurizio Martina, Guido Masera:
A Network-on-Chip-based turbo/LDPC decoder architecture. DATE 2012: 1525-1530 - [c53]Muhammad Awais, Marco Vacca, Mariagrazia Graziano, Guido Masera:
FFT implementation using QCA. ICECS 2012: 741-744 - [c52]Lorenzo Guerrieri, Paola Bisaglia, Maurizio Martina, Guido Masera:
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation. ISTC 2012: 180-184 - 2011
- [j30]Maurizio Martina, Guido Masera:
Multiplierless Mumford and Shah Functional Implementation. Circuits Syst. Signal Process. 30(3): 567-586 (2011) - [j29]Micaela Troglia Gamba, Guido Masera:
Look-ahead sphere decoding: algorithm and VLSI architecture. IET Commun. 5(9): 1275-1285 (2011) - [j28]Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi:
On chip interconnects for multiprocessor turbo decoding architectures. Microprocess. Microsystems 35(2): 167-181 (2011) - [j27]Maurizio Martina, Guido Masera:
State Metric Compression Techniques for Turbo Decoder Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 1119-1128 (2011) - [c51]Muhammad Awais, Ashwani Singh, Guido Masera:
Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications. ACC (2) 2011: 374-385 - [c50]Carlo Condo, Guido Masera:
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. DASIP 2011: 261-268 - [c49]Muhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera:
A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder. DSD 2011: 340-347 - [i7]Maurizio Martina, Guido Masera:
Improving Network-on-Chip-based turbo decoder architectures. CoRR abs/1105.1014 (2011) - [i6]Carlo Condo, Guido Masera:
A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture. CoRR abs/1105.2624 (2011) - 2010
- [j26]Maurizio Martina, Guido Masera, Gianluca Piccinini:
Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits Devices Syst. 4(2): 159-167 (2010) - [j25]Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera:
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. Microprocess. Microsystems 34(7-8): 316-328 (2010) - [j24]Maurizio Martina, Guido Masera:
Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2776-2789 (2010) - [c48]Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera:
ALOE-Based Flexible LDPC Decoder. DSD 2010: 314-320 - [c47]Bin Wu, Guido Masera:
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. DSD 2010: 737-744 - [c46]Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca:
Thermal Control for Crossbar-Based Input-Queued Switches. GLOBECOM 2010: 1-5 - [i5]Maurizio Martina, Guido Masera:
VLSI Architectures for WIMAX Channel Decoders. CoRR abs/1001.4694 (2010) - [i4]Bin Wu, Guido Masera:
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder. CoRR abs/1006.4030 (2010)
2000 – 2009
- 2009
- [j23]Ashwani Singh, Ali Al Ghouwayel, Guido Masera, Emmanuel Boutillon:
A new performance evaluation metric for sub-optimal iterative decoders. IEEE Commun. Lett. 13(7): 513-515 (2009) - [j22]Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera, Maurizio Martina:
On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator. IEEE Commun. Lett. 13(7): 522-524 (2009) - [j21]Maurizio Martina, Mario Nicola, Guido Masera:
Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder. J. Circuits Syst. Comput. 18(3): 535-564 (2009) - [j20]Andrea Molino, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Terreno, Giorgio Pasquettaz, Giuseppe D'Angelo:
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring. Microprocess. Microsystems 33(3): 179-190 (2009) - [j19]Simone Zezza, Saeid Nooshabadi, Maurizio Martina, Guido Masera:
Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 19(4): 591-596 (2009) - [j18]Barbara Cerato, Guido Masera, Emanuele Viterbo:
Decoding the Golden Code: A VLSI Design. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 156-160 (2009) - [c45]Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel:
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD 2009: 582-589 - [c44]Simone Zezza, Guido Masera, Saeid Nooshabadi:
A feasible VLSI engine for soft-input-soft-output for joint source channel codes. ICIP 2009: 2669-2672 - [c43]Micaela Troglia Gamba, Guido Masera:
Look-Ahead Sphere Decoding: Algorithm and performance evaluation. ISWCS 2009: 151-155 - [i3]Maurizio Martina, Guido Masera:
Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures. CoRR abs/0909.1876 (2009) - 2008
- [j17]Barbara Cerato, Guido Masera, Emanuele Viterbo:
Decoding the golden space-time trellis coded modulation. IEEE Commun. Lett. 12(8): 569-571 (2008) - [j16]Maurizio Martina, Mario Nicola, Guido Masera:
Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding. IEEE Commun. Lett. 12(11): 846-848 (2008) - [j15]Fabrizio Vacca, Libero Dinoi, Guido Masera:
Design of a VLSI Decoder for Partially Structured LDPC Codes. Int. J. Digit. Multim. Broadcast. 2008: 245305:1-245305:12 (2008) - [j14]Maurizio Martina, Mario Nicola, Guido Masera:
A Flexible UMTS-WiMax Turbo Decoder Architecture. IEEE Trans. Circuits Syst. II Express Briefs 55-II(4): 369-373 (2008) - [j13]Maurizio Martina, Guido Masera:
Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 494 (2008) - [j12]Barbara Cerato, Guido Masera, Emanuele Viterbo:
Enabling VLSI Processing Blocks for MIMO-OFDM Communications. VLSI Design 2008: 351962:1-351962:10 (2008) - [c42]Simone Zezza, Guido Masera:
VLSI implementation of SISO arithmetic decoders for joint source channel coding. DATE 2008: 1075-1078 - [c41]Simone Zezza, Maurizio Martina, Guido Masera, Saeid Nooshabadi:
Error resilient JPEG2000 decoding for wireless applications. ICIP 2008: 2016-2019 - 2007
- [j11]Guido Masera, Federico Quaglio, Fabrizio Vacca:
Implementation of a Flexible LDPC Decoder. IEEE Trans. Circuits Syst. II Express Briefs 54-II(6): 542-546 (2007) - [j10]Maurizio Martina, Guido Masera:
Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture. IEEE Trans. Circuits Syst. II Express Briefs 54-II(9): 770-774 (2007) - [c40]Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D'Angelo, Giorgio Pasquettaz:
Real-time implementation of a time-frequency analysis scheme. ACM Great Lakes Symposium on VLSI 2007: 180-183 - [c39]Maurizio Martina, Guido Masera:
Flexible blocks for high throughput serially concatenated convolutional codes. ACM Great Lakes Symposium on VLSI 2007: 184-187 - [c38]Barbara Cerato, Guido Masera, Peter Nilsson:
Hardware architecture for matrix factorization in mimo receivers. ACM Great Lakes Symposium on VLSI 2007: 196-199 - [c37]Alberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera:
Beyond 3G wireless communication system prototype. ACM Great Lakes Symposium on VLSI 2007: 335-340 - [i2]Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. CoRR abs/0710.4840 (2007) - [i1]Barbara Cerato, Guido Masera, Emanuele Viterbo:
Decoding the Golden Code: a VLSI design. CoRR abs/0711.2383 (2007) - 2006
- [j9]Maurizio Martina, Guido Masera:
Mumford and Shah Functional: VLSI Analysis and Implementation. IEEE Trans. Pattern Anal. Mach. Intell. 28(3): 487-494 (2006) - [j8]Maurizio Martina, Guido Masera:
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1289-1293 (2006) - [c36]Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante:
A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51 - [c35]Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera:
Interconnection framework for high-throughput, flexible LDPC decoders. DATE Designers' Forum 2006: 124-129 - [c34]Maurizio Martina, Guido Masera, Luca Fanucci, Sergio Saponara:
Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding. EUSIPCO 2006: 1-5 - [c33]Oguzhan Atak, Abdullah Atalar, Erdal Arikan, Harold Ishebabi, David Kammler, Gerd Ascheid, Heinrich Meyr, Mario Nicola, Guido Masera:
Design of Application Specific Processors for the Cached FFT Algorithm. ICASSP (3) 2006: 1028-1031 - [c32]Barbara Cerato, Guido Masera, Emanuele Viterbo:
A VLSI Decoder for the Golden code. ICECS 2006: 549-552 - [c31]Giorgio Pioppo, Rashid Ansari, Ashfaq A. Khokhar, Guido Masera:
Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information. ICIP 2006: 3153-3156 - [c30]Simone Zezza, Marco Grangetto, Maurizio Martina, Fabrizio Vacca, Guido Masera:
Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. MobiMedia 2006: 3 - [c29]Mario Nicola, Alberto Dassatti, Guido Masera, Andrea Concil, Angelo Poloni:
Mixed hardware-software testbed for IEEE-802.11n. TRIDENTCOM 2006 - 2005
- [c28]Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni:
High Performance Channel Model Hardware Emulator for 802.11n. FPT 2005: 303-304 - [c27]Maurizio Martina, Guido Masera:
Low-complexity, efficient 9/7 wavelet filters implementation. ICIP (3) 2005: 1000-1003 - [c26]Andrea Molino, Fabrizio Vacca, Guido Masera:
Optimized CORDIC core for frequency-domain motion estimation. ICIP (3) 2005: 1072-1075 - [c25]Andrea Molino, Fabrizio Vacca, Guido Masera:
Design and implementation of phase correlation based motion estimator. SoCC 2005: 291-294 - 2004
- [j7]Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. 35(10): 849-857 (2004) - [j6]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 349-358 (2004) - [c24]Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. DATE 2004: 228-233 - [c23]Maurizio Martina, Guido Masera:
A statistical model for estimating the effect of process variations on crosstalk noise. SLIP 2004: 115-120 - 2003
- [j5]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. 34(12): 1175-1185 (2003) - [j4]Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. 35(2): 137-153 (2003) - [c22]Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni:
Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA 2003: 246 - [c21]Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100 - [c20]M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130 - 2002
- [j3]Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni:
Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 279-285 (2002) - [c19]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL 2002: 332-339 - [c18]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Reconfigurable DSP IP for multimedia applications. ICASSP 2002: 4179 - [c17]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP 2002: 211-218 - [c16]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS 2002: 855-858 - [c15]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni:
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208 - 2001
- [c14]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
JPEG 2000: finite precision representation and hardware implications. ICECS 2001: 875-878 - [c13]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Reconfigurable coprocessor based JPEG 2000 implementation. ICECS 2001: 1227-1230 - [c12]Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290 - [c11]Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Hierarchical power supply noise evaluation for early power grid design prediction. SLIP 2001: 183-188 - [c10]Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design 2001: 524-530 - 2000
- [c9]Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A 50 Mbit/s Iterative Turbo-Decoder. DATE 2000: 176-180 - [c8]Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A high accuracy-low complexity model for CMOS delays. ISCAS 2000: 455-458 - [c7]Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Noise Safety Design Methodologies. ISQED 2000: 157-
1990 – 1999
- 1999
- [j2]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 369-379 (1999) - [c6]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics 1999: 51-54 - [c5]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI 1999: 82-85 - [c4]Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A global optimization tool for CMOS logic circuits. ICECS 1999: 1671-1674 - 1998
- [c3]A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A 500 MHz 2d-DWT VLSI processor. EUSIPCO 1998: 1-4 - 1996
- [c2]F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO 1996: 1-4 - [c1]Mariana-Eugenia Petre, Guido Masera:
A Parametrical Architecture for Reed-Solomon Decoders. Great Lakes Symposium on VLSI 1996: 81-
1980 – 1989
- 1989
- [j1]Sergio Benedetto, Marco Ajmone Marsan, Guido Masera, Gabriella Olmo, Z. Zhang:
Encoded 16-PSK: a study for the receiver design. IEEE J. Sel. Areas Commun. 7(9): 1381-1391 (1989)
Coauthor Index
[j75] [c94] [c93] [i21] [i20] [j74] [j73] [j72] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [i19] [c85] [c84] [c83] [c82] [c81] [i17] [i16] [i15] [j71] [j70] [c80] [c79] [c78] [i14] [i13] [i12] [j69] [j68] [j67] [j66] [j65] [c77] [c76] [c75] [c74] [i11] [i10] [j64] [j62] [c73] [i9] [c72] [c71] [j60] [j59] [c69] [c68] [c67] [c66] [j58] [c65] [c64] [j55] [j54] [j52] [j51] [c63] [c62] [c61] [j50] [j48] [j46] [j45] [j44] [c58] [j40] [j39] [c57] [c55] [j38] [j36] [j35] [j34] [j33] [c54] [c52] [j30] [j28] [j27] [i7] [j26] [j25] [j24] [i5] [j22] [j21] [j20] [j19] [i3] [j16] [j14] [j13] [c41] [j10] [c40] [c39] [j9] [j8] [c36] [c34] [c30] [c27] [c23] [j4] [c22] [c19] [c18] [c17] [c16] [c14] [c13]
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