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ORCIDAnas Razzaq Ghumman
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2020 – today
- 2022
[j6]Anas Razzaq
, Sajjad Rostami Sani, Andy Gean Ye:
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs. Integr. 86: 30-43 (2022)- [c2]Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye:
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. FCCM 2022: 1-9 - 2021
- [j5]Anas Razzaq, Andy Gean Ye:
Static power model for CMOS and FPGA circuits. IET Comput. Digit. Tech. 15(4): 263-278 (2021) - [j4]Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye:
Designing efficient FPGA tiles for power-constrained ultra-low-power applications. Integr. 78: 124-134 (2021) - 2020
- [c1]Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye:
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. FPL 2020: 214-219
2010 – 2019
- 2019
- [j3]Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera:
LDPC check node implementation using reversible logic. IET Circuits Devices Syst. 13(4): 443-455 (2019) - 2018
- [j2]Anas Razzaq Ghumman, Shabbir Majeed Chaudhry:
A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS. Circuits Syst. Signal Process. 37(4): 1452-1478 (2018) - 2016
- [j1]Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry:
A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm. Circuits Syst. Signal Process. 35(9): 3113-3134 (2016)
Coauthor Index
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