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ORCID13th PATMOS 2003: Torino, Italy
- Jorge Juan-Chico, Enrico Macii:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings. Lecture Notes in Computer Science 2799, Springer 2003, ISBN 3-540-20074-6
Keynote Speech
- Andrea Cuomo:
Architectural Challenges for the Next Decade Integrated Platforms. 1
Gate-Level Modeling and Design
- G. Privitera, Francesco Pessolano:
Analysis of High-Speed Logic Families. 2-10 - Pradeep Varma, Ashutosh Chakraborty:
Low-Voltage, Double-Edge-Triggered Flip Flop. 11-20 - Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. 21-30 - Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo:
State Encoding for Low-Power FSMs in FPGA. 31-40
Low Level Modeling and Characterization
- Tim Schoenauer, Jörg Berthold, Christoph Heer:
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies. 41-50 - José Luis Rosselló, Jaume Segura
:
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. 51-59 - Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
CMOS Gate Sizing under Delay Constraint. 60-69 - E. Seebacher, Gerhard Rappitsch, H. Höller:
Process Characterization for Low VTH and Low Power Design. 70-79 - Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez:
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. 80-89
Interconnect Modeling and Optimization
- Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. 90-100 - Jérôme Lescot, François J. R. Clément:
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. 101-110 - Sampo Tuuna, Jouni Isoaho:
Estimation of Crosstalk Noise for On-Chip Buses. 111-120 - M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. 121-130 - Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel:
Interconnect Driven Low Power High-Level Synthesis. 131-140
Asynchronous Techniques
- Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim:
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap. 141-150 - Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. 151-160 - Milos Krstic, Eckhard Grass:
New GALS Technique for Datapath Architectures. 161-170 - João Leonardo Fragoso, Gilles Sicard, Marc Renaudin:
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. 171-180 - Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
Statistic Implementation of QDI Asynchronous Primitives. 181-191
Keynote Speech
- Antun Domic:
The Emergency of Design for Energy Efficiency: An EDA Perspective. 192
Industrial Session
- Jean Oudinot:
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. 193 - Louis Scheffer:
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. 194 - Power Management in Synopsys Galaxy Design Platform. 195
- Open Multimedia Platform for Next-Generation Mobile Devices. 196
RTL Power Modeling and Memory Optimisation
- B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu:
Statistical Power Estimation of Behavioral Descriptions. 197-207 - Maurizio Bruno, Alberto Macii, Massimo Poncino:
A Statistic Power Model for Non-synthetic RTL Operators. 208-218 - Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose:
Energy Efficient Register Renaming. 219-228 - S. Cservany, Jean-Marc Masgonty, Christian Piguet:
Stand-by Power Reduction for Storage Circuits. 229-238 - José L. Ayala, Marisa Luisa López-Vallejo:
A Unified Framework for Power-Aware Design of Embedded Systems. 239-248
High-Level Modeling
- Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. 249-258 - Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy:
High Level Area and Current Estimation. 259-268 - Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Switching Activity Estimation in Non-linear Architectures. 269-278 - Spiridon Nikolaidis, Nikolaos Kavvadias, Theodore Laopoulos, Labros Bisdounis, Spyros Blionas:
Instruction Level Energy Modeling for Pipelined Processors. 279-288 - Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins:
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. 289-298
Power Efficient Technologies and Designs
- Vineela Manne, Akhilesh Tyagi:
An Adiabatic Charge Pump Based Charge Recycling Design Style. 299-308 - Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel:
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. 309-318 - Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Response Time Accelerator with Full Resolution for LCD Panel. 319-327 - Vissarion Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor:
Memory Compaction and Power Optimization for Wavelet-Based Coders. 328-337 - Emil Hjalmarson, Robert Hägglund, Lars Wanhammar:
Design Space Exploration and Trade-Offs in Analog Amplifier Design. 338-347
Keynote Speech
- Ricardo Augusto da Luz Reis:
Power and Timing Driven Physical Design Automation. 348-357
Communication Modeling and Design
- Ramesh Karri, Piyush Mishra:
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. 358-368 - Andrea Acquaviva, Tajana Simunic, Vinay Deolalikar, Sumit Roy:
Remote Power Control of Wireless Network Interfaces. 369-378 - Frank Gilbert, Norbert Wehn:
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders. 379-388 - Seyed Reza Abdollahi, Bertan Bakkaloglu, S. K. Hosseini:
A Fully Digital Numerical-Controlled-Oscillator. 389-398
Low Power Issues in Processors and Multimedia
- Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy Optimization of High-Performance Circuits. 399-408 - Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor:
Instruction Buffering Exploration for Low Energy Embedded Processors. 409-419 - Amirali Baniasadi:
Power-Aware Branch Predictor Update for High-Performance Processors. 420-429 - Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas:
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. 430-439 - Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney:
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder. 440-450
Poster Session
- Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Metric Definition for Circuit Speed Optimization. 451-460 - Grzegorz Tosik, Frédéric Gaffiot, Zbigniew Lisik, Ian O'Connor, Faress Tissafi-Drissi:
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies. 461-470 - Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari:
An Asynchronous Viterbi Decoder for Low-Power Applications. 471-480 - Eugeni Isern, Miquel Roca, Francesc Moll:
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits. 481-490 - Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. 491-500 - David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. 501-510 - Dongsheng Wang, Peter Suaris, Nan-Chi Chou:
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. 511-519 - Byung-Soo Choi, Dong-Ik Lee:
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. 520-529 - Akihito Sakanaka, Toshinori Sato:
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. 530-539 - Andrea Acquaviva, Alessandro Bogliolo:
A Bottom-Up Approach to On-Chip Signal Integrity. 540-549 - Wen-Tsong Shiue, Weetit Wanalertlak:
Advanced Cell Modeling Techniques Based on Polynomial Expressions. 550-558 - Paul Flugger:
RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches. 559-568 - Anatoly Prihozhy, Marco Mattavelli, Daniel Mlynek:
Data Dependences Critical Path Evaluation at C/C++ System Level Description. 569-579 - Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién:
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. 580-589 - Chee Lee, Wen-Tsong Shiue:
Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power. 590-598 - Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Cache with Successive Tag Comparison Algorithm. 599-606 - Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis:
FPGA Architecture Design and Toolset for Logic Implementation. 607-616 - María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. 617-627
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