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ORCIDIntegration, Volume 50
Volume 50, June 2015
- Zhenyu Wu, Changhao Yan, Xuan Zeng, Sheng-Guo Wang:
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method. 1-15 - Hooman Farkhani, Ali Peiravi, Farshad Moradi
:
A new write assist technique for SRAM design in 65 nm CMOS technology. 16-27 - Prakash Harikumar, J. Jacob Wikner:
A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer. 28-38 - Guillaume Hubert, Laurent Artola, D. Regis:
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation. 39-47 - Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A current monitoring technique for IDDQ testing in digital integrated circuits. 48-60 - Rajit Karmakar, Santanu Chattopadhyay:
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. 61-73 - Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández:
On the convex formulation of area for slicing floorplans. 74-80 - Marzieh Morshedzadeh, Ali Jahanian, Payam Pourashraf:
Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage. 81-90 - Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram:
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. 91-106 - Chunhong Chen, Ran Xiao:
A fast model for analysis and improvement of gate-level circuit reliability. 107-115 - Giovanni B. Vece, Massimo Conti, Simone Orcioni:
Transaction-level power analysis of VLSI digital systems. 116-126 - Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Power supply noise in accurate delay model for the sub-threshold domain. 127-136 - Masoud Daneshtalab, Nader Bagherzadeh, Hamid Sarbazi-Azad:
On-chip parallel and network-based systems. 137-138 - Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera:
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. 139-146 - Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab:
An efficient runtime power allocation scheme for many-core systems inspired from auction theory. 147-157 - Abderrahim Chariete, Mohamed Bakhouya, Jaafar Gaber, Maxime Wack:
A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs. 158-172 - Ramin Bashizade, Hamid Sarbazi-Azad:
P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs. 173-182 - Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh:
On the design of hybrid routing mechanism for mesh-based network-on-chip. 183-192 - Mehdi Modarressi, Nasibeh Teimouri, Hamid Sarbazi-Azad:
Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths. 193-204
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