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"PERI: A Posit Enabled RISC-V Core."
Sugandha Tiwari et al. (2019)
- Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti:
PERI: A Posit Enabled RISC-V Core. CoRR abs/1908.01466 (2019)
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