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ORCID"PERI: A Configurable Posit Enabled RISC-V Core."
Sugandha Tiwari et al. (2021)
- Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti:
PERI: A Configurable Posit Enabled RISC-V Core. ACM Trans. Archit. Code Optim. 18(3): 25:1-25:26 (2021)
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