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Books and Theses
- 2002
[b1]Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra:
Test Resource Partitioning for System-on-a-Chip. Frontiers in electronic testing 20, Kluwer / Springer 2002, ISBN 978-1-4020-7119-5, pp. I-XII, 1-232
Journal Articles
- 2012
- [j14]Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar:
Physically-Aware N-Detect Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 308-321 (2012) - 2009
- [j13]Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty
, Vikram Iyengar:
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 587-592 (2009) - 2005
- [j12]Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski:
Test planning for modular testing of hierarchical SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 435-448 (2005) - 2004
- [j11]Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty:
SOC test planning using virtual test access architectures. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1263-1276 (2004) - 2003
- [j10]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003) - [j9]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 635-643 (2003) - 2002
- [j8]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electron. Test. 18(2): 213-230 (2002) - [j7]Vikram Iyengar, Krishnendu Chakrabarty:
Test Bus Sizing for System-on-a-Chip. IEEE Trans. Computers 51(5): 449-459 (2002) - [j6]Vikram Iyengar, Krishnendu Chakrabarty:
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1088-1094 (2002) - 2000
- [j5]Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick:
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electron. Test. 16(1-2): 13-27 (2000) - [j4]Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 633-636 (2000) - 1999
- [j3]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electron. Test. 15(1-2): 97-114 (1999) - 1998
- [j2]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
Huffman encoding of test sets for sequential circuits. IEEE Trans. Instrum. Meas. 47(1): 21-25 (1998) - 1997
- [j1]Vikram Iyengar, Krishnendu Chakrabarty:
An Efficient Finite-State Machine Implementation of Huffman Decoders. Inf. Process. Lett. 64(6): 271-275 (1997)
Conference and Workshop Papers
- 2010
- [c31]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise:
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733 - 2008
- [c30]Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar:
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. ITC 2008: 1-9 - 2007
- [c29]Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar:
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828 - [c28]Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah:
Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD 2007: 405-412 - [c27]Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland:
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS 2007: 173-178 - 2006
- [c26]Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, Frank Woytowich, Bob Bassett:
Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs. CICC 2006: 567-570 - [c25]Vikram Iyengar, Gary Grise, Mark Taylor:
A flexible and scalable methodology for GHz-speed structural test. DAC 2006: 314-319 - [c24]Chunsheng Liu, Vikram Iyengar:
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. DATE 2006: 652-657 - [c23]Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich:
Performance verification of high-performance ASICs using at-speed structural test. ACM Great Lakes Symposium on VLSI 2006: 247-252 - [c22]Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich:
At-Speed Structural Test For High-Performance ASICs. ITC 2006: 1-10 - [c21]Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51 - 2005
- [c20]Vikram Iyengar, Phil Nigh:
Defect-Oriented Test for Ultra-Low DPM. Asian Test Symposium 2005: 455 - [c19]Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar:
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. DFT 2005: 552-562 - [c18]Matthew A. Csencsits, Bryan A. Jones, William McMahan, Vikram Iyengar, Ian D. Walker:
User interfaces for continuum robot arms. IROS 2005: 3123-3130 - [c17]Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota:
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. VTS 2005: 349-354 - 2003
- [c16]Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty:
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC 2003: 738-743 - [c15]Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty:
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. DATE 2003: 11188-11190 - [c14]Vikram Iyengar, Anshuman Chandra:
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. DFT 2003: 511-518 - [c13]Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar:
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. VTS 2003: 299-312 - 2002
- [c12]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320- - [c11]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690 - [c10]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498 - [c9]Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty:
A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528 - [c8]Sandeep Koranne, Vikram Iyengar:
On the Use of k-tuples for SoC Test Schedule Representation. ITC 2002: 539-548 - [c7]Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168 - [c6]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258 - 2001
- [c5]Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032 - [c4]Vikram Iyengar, Krishnendu Chakrabarty:
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. VTS 2001: 368-374 - 2000
- [c3]Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara:
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA 2000 - 1999
- [c2]Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27 - 1998
- [c1]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423
Reference Works
- 1999
- [r1]Vikram Iyengar, Elizabeth M. Rudnick:
Microprocessor Design Verification. The VLSI Handbook 1999
Coauthor Index
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