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2010 – 2019
- 2013
[c6]Jin Wang, Bo Yun, Pingli Huang, Yu-Ao Liu:
Applying Threshold SMOTE Algoritwith Attribute Bagging to Imbalanced Datasets. RSKT 2013: 221-228- [c5]Jin Wang, Pingli Huang, Kai-wei Sun, Bao-lin Cao, Rui Zhao:
Ensemble of Cost-Sensitive Hypernetworks for Class-Imbalance Learning. SMC 2013: 1883-1888 - 2012
- [c4]Wenbo Liu, Pingli Huang, Yun Chiu
:
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. CICC 2012: 1-4 - 2011
- [b1]Pingli Huang:
SHA-less pipeline ADC design with sampling clock skew calibration. University of Illinois Urbana-Champaign, USA, 2011 - [j2]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. IEEE J. Solid State Circuits 46(8): 1893-1903 (2011) - [j1]Wenbo Liu, Pingli Huang, Yun Chiu:
A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. IEEE J. Solid State Circuits 46(11): 2661-2672 (2011) - 2010
- [c3]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4 - [c2]Wenbo Liu, Pingli Huang, Yun Chiu:
A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR. ISSCC 2010: 380-381
2000 – 2009
- 2007
- [c1]Pingli Huang, Yun Chiu:
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ISCAS 2007: 1241-1244
Coauthor Index
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