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ORCIDHiroaki Yoda
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2010 – 2019
- 2018
[c7]Naoharu Shimomura, Hiroaki Yoda, Tomoaki Inokuchi, Katsuhiko Koi, Hideyuki Sugiyama, Yushi Kato, Yuichi Ohsawa, Altansargai Buyandalai, Satoshi Shirotori
, Soichi Oikawa, Mariko Shimizu, Mizue Ishikawa, Tiwari Ajay, Atsushi Kurobe:
High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design Windows. VLSI Circuits 2018: 83-84- 2017
- [c6]Hideyuki Sugiyama, Hiroaki Yoda, Katsuhiko Koi, Soichi Oikawa, Buyandalai Altansargai, Tomoaki Inokuchi, Satoshi Shirotori, Mariko Shimizu, Yuichi Kato, Yuichi Ohsawa, Mizue Ishikawa, Ajay Tiwari, Naoharu Shimomura, Yoshiaki Saito, Atsushi Kurobe:
High-speed voltage-control spintronics memory focused on reduction in write current. NVMTS 2017: 1-5 - 2016
- [i1]Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda:
High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. CoRR abs/1606.03147 (2016) - 2015
- [c5]Hiroaki Yoda, E. Kitagawa, Naoharu Shimomura, S. Fujita, Minoru Amano:
The progresses of MRAM as a memory to save energy consumption and its potential for further reduction. VLSIC 2015: 104- - 2010
- [c4]Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe:
A 64Mb MRAM with clamped-reference and adequate-reference schemes. ISSCC 2010: 258-259
2000 – 2009
- 2008
- [c3]Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi:
A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. DFT 2008: 507-515 - 2006
- [c2]Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda:
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC 2006: 477-486 - 2003
- [c1]Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda:
Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. CICC 2003: 399-402
Coauthor Index
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